AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet - Page 457

• Manufacturer Part Number: AT90USB1287-AU
• Description: IC AVR MCU 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR USB
• No. Of I/o's: 48
• Eeprom Memory Size: 4KB
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB1287-16AU; AT90USB1287-16AU

24 Analog Comparator .............................................................................. 310
25 Analog to Digital Converter - ADC ...................................................... 313
26 JTAG Interface and On-chip Debug System ...................................... 332
27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 338
7593K–AVR–11/09
23.9 Remote Wake-Up detection ..............................................................................293
23.10 USB Pipe Reset ...............................................................................................293
23.11 Pipe Data Access ............................................................................................293
23.12 Control Pipe management ...............................................................................294
23.13 OUT Pipe management ...................................................................................294
23.14 IN Pipe management .......................................................................................295
23.15 Interrupt system ...............................................................................................296
23.16 Registers .........................................................................................................297
24.1 Analog Comparator Multiplexed Input ...............................................................312
25.1 Features ............................................................................................................313
25.2 Operation ...........................................................................................................314
25.3 Starting a Conversion ........................................................................................315
25.4 Prescaling and Conversion Timing ....................................................................316
25.5 Changing Channel or Reference Selection .......................................................319
25.6 ADC Noise Canceler .........................................................................................320
25.7 ADC Conversion Result .....................................................................................324
25.8 ADC Register Description ..................................................................................326
26.1 Overview ............................................................................................................332
26.2 Test Access Port – TAP ....................................................................................332
26.3 TAP Controller ...................................................................................................334
26.4 Using the Boundary-scan Chain ........................................................................335
26.5 Using the On-chip Debug System .....................................................................335
26.6 On-chip Debug Specific JTAG Instructions .......................................................336
26.7 On-chip Debug Related Register in I/O Memory ...............................................337
26.8 Using the JTAG Programming Capabilities .......................................................337
26.9 Bibliography .......................................................................................................337
27.1 Features ............................................................................................................338
27.2 System Overview ...............................................................................................338
27.3 Data Registers ...................................................................................................338
27.4 Boundary-scan Specific JTAG Instructions .......................................................340
27.5 Boundary-scan Related Register in I/O Memory ...............................................341
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