AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet - Page 379

• Manufacturer Part Number: AT90USB1287-AU
• Description: IC AVR MCU 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR USB
• No. Of I/o's: 48
• Eeprom Memory Size: 4KB
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB1287-16AU; AT90USB1287-16AU

29.6.15
7593K–AVR–11/09
Parallel Programming Characteristics
Figure 29-7. Parallel Programming Timing, Including some General Timing Requirements
Figure 29-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 29-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
XTAL1
DATA
PAGEL
(DATA, XA0/1, BS1, BS2)
XTAL1
BS1
XA0
XA1
DATA
OE
BS1
XA0
XA1
1. The timing requirements shown in
ing operation.
Data & Contol
Timing Requirements
RDY/BSY
ADDR0 (Low Byte)
LOAD ADDRESS
ADDR0 (Low Byte)
LOAD ADDRESS
PAGEL
(LOW BYTE)
XTAL1
(LOW BYTE)
WR
t
XLOL
t
OLDV
t
t
BVPH
DVXH
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 29-7
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
t
BVDV
(i.e., t
t
BVWL
(HIGH BYTE)
LOAD DATA
DATA (High Byte)
DVXH
(HIGH BYTE)
READ DATA
t
DATA (High Byte)
WLWH
t
XLPH
WLRL
LOAD DATA
, t
XHXL
AT90USB64/128
, and t
t
OHDZ
t
PLXH
t
WLBX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
) also apply to load-
ADDR1 (Low Byte)
ADDR1 (Low Byte)
t
WLRH
(1)
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