AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet - Page 32

• Manufacturer Part Number: AT90USB1287-AU
• Description: IC AVR MCU 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR USB
• No. Of I/o's: 48
• Eeprom Memory Size: 4KB
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB1287-16AU; AT90USB1287-16AU

5.5.4
5.5.5
32
AT90USB64/128
Pull-up and Bus-keeper
Timing
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in
on page
these lines are tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
XMEM interface provides four different wait-states as shown in
sider the timing specification of the External Memory device before selecting the wait-state. The
most important parameters are the access time for the external memory compared to the set-up
requirement. The access time for the External Memory is defined to be the time from receiving
the chip select/address until the data of this address actually is driven on the bus. The access
time cannot exceed the time from the ALE pulse must be asserted low until data is stable during
a read sequence (See t
409). The different wait-states are set up in software. As an additional feature, it is possible to
divide the external memory space in two sectors with individual wait-state settings. This makes it
possible to connect two different memory devices with different timing requirements to the same
XMEM interface. For XMEM interface timing details, please refer to Tables 30-6 through Tables
30-13 and
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 5-6.
Note:
System Clock (CLK
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
35. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
Figure 30-7
SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction
accesses the RAM (internal or external).
External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
DA7:0
A15:8
CPU
ALE
WR
RD
)
to
LLRL
Prev. addr.
Prev. data
Prev. data
Prev. data
Figure 30-10
+ t
RLRH
T1
- t
DVRH
in the
in Tables 30-6 through Tables 30-13 on pages 407 -
Address
Address
“External Data Memory Timing” on page
Address
“External Memory Control Register B – XMCRB”
T2
XX
Address
T3
Data
Data
Data
Table
5-5. It is important to con-
T4
7593K–AVR–11/09
407.