ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet

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EEPROM, ADC, 8/12/16-bit timers, SPI and I²C interface Features ■ Memories – 8 Kbytes single voltage extended Flash (XFlash) program memory with Read-out protection In-circuit programming and in-application programming (ICP and IAP) Endurance: 10K write/erase cycles guaranteed Data retention: ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITE49K2 6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITE49K2 10.7.1 10.7.2 11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 11.5.3 11.5.4 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITE49K2 12.1.6 12.1.7 12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 13.9.2 13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITE49K2 List of tables Table 1. ST7LITE49K2 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables 2 Table 49 register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITE49K2 Table 101. ADC accuracy with VDD = 2 ...

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List of figures List of figures Figure 1. ST7LITE49K2 general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST7LITE49K2 Figure 49. Block diagram of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 101. R resistance versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . 215 pu Figure 102. I ...

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ST7LITE49K2 1 Description The ST7LITE49K2 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE49K2 features Flash memory with byte-by-byte In-Circuit Programming (ICP) and ...

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Description Figure 1. ST7LITE49K2 general block diagram CLKIN OSC_IN OSC_OUT RESET 16/245 PLL 8 MHz -> 32 MHz / 2 Ext. OSC / 2 1 MHz to Internal 16 MHz clock Int. 8 MHz RC OSC ...

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ST7LITE49K2 2 Pin description Figure 2. 32-pin SDIP package pinout COMPOUTA/BREAK1/PC7 ATPWM2/MCO/PA4(HS) Note 1: Available on 8K version only Figure 3. 32-pin LQFP 7x7 package pinout ATPWM1/PA3(HS) ATPWM2/MCO/PA4(HS) ATPWM3/PA5(HS) I2CDATA/PA6(HS) I2CCLK/PA7(HS) 1 ei2 PA0(HS)/COMPINA- 2 ei2 ATIC/PA1(HS) 3 ATPWM0/PA2(HS) 4 ...

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Pin description Legend / Abbreviations for Type input output supply In/Output level: C Output level high sink (on N-buffer only) Port and control configuration: ● Input: float = floating, wpu ...

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ST7LITE49K2 Table 2. ST7LITE49K2 device pin description Pin number Pin name 14 18 PB0/AIN0 15 19 PB1/AIN1/CLKIN 16 20 PB2/AIN2 17 21 PB3/AIN3/MOSI 18 22 PB4/AIN4/MISO PB5/AIN5 EXTCLK_A/ COMPOUTB 20 24 PB6/AIN6/SCK PB7/AIN7/SS OCMP2_A PC0/AIN8/ 22 ...

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Pin description Table 2. ST7LITE49K2 device pin description Pin number Pin name PC4/LTIC COMPINB- PC5/COMPINB BREAK2 28 32 PC6/COMPINA+ PC7/BREAK1 COMPOUTA PA0 /COMPINA /OCMP1_A 31 3 PA1(HS)/ATIC 32 4 PA2(HS)/ATPWM0 I/O 1. ...

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ST7LITE49K2 3 Register and memory mapping As shown in Figure registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of Flash program memory. The RAM ...

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Register and memory mapping Table 3. Hardware register map Address Block Register label 0011h ATCSR 0012h CNTR1H 0013h CNTR1L 0014h ATR1H 0015h ATR1L 0016h PWMCR 0017h PWM0CSR 0018h PWM1CSR 0019h PWM2CSR 001Ah PWM3CSR 001Bh DCR0H 001Ch DCR0L AUTO- 001Dh DCR1H ...

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ST7LITE49K2 Table 3. Hardware register map Address Block Register label RCCR 003Bh SICSR 003Ch Clock and Reset 003Dh AVDTHCR 003Eh to 0047h 0048h AWUCSR AWU 0049h AWUPR 004Ah DMCR 004Bh DMSR 004Ch DMBK1H (2) 004Dh DM DMBK1L 004Eh DMBK2H 004Fh ...

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Register and memory mapping 1. Legend: x=undefined, R/W=read/write. 2. For a description of the Debug Module registers, see ICC protocol reference manual. Figure 4. ST7LITE49K2 memory map 0000h HW registers 007Fh 0080h RAM (384 bytes) 01FFh 0200h Reserved 0FFFh 1000h ...

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ST7LITE49K2 4 Flash programmable memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices ...

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Flash programmable memory Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In-application programming (IAP) This ...

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ST7LITE49K2 during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Figure 5. Typical ICC Interface (See Note 3) APPLICATION POWER SUPPLY PROGRAMMING TOOL ICC CONNECTOR ICC ...

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Flash programmable memory 4.5 Memory protection There are two different types of memory protection: Read-Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read-out protection Read-Out Protection, when selected provides a protection against program memory content extraction and ...

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ST7LITE49K2 5 Data EEPROM 5.1 Introduction The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 Main features ● ...

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Data EEPROM 5.3 Memory access The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in different memory access modes. 5.3.1 Read operation (E2LAT=0) The EEPROM can be read ...

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ST7LITE49K2 Figure 8. Data EEPROM write operation ROW DEFINITION Byte 1 E2LAT bit Set by USER application E2PGM bit programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. ...

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Data EEPROM 5.6 Data EEPROM read-out protection The read-out protection is enabled through an option bit (see When this option is selected, the programs and data stored in the EEPROM memory are protected against Read-out (including a re-write protection). In ...

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ST7LITE49K2 6 Central processing unit 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ● 17 ...

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Central processing unit 6.3.1 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 Index registers (X and Y) In indexed addressing ...

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ST7LITE49K2 Bit Interrupt mask bit This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. ...

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Central processing unit * Table 4. Interrupt software priority truth table 6.3.5 Stack pointer (SP) Reset value: 01FFh The Stack Pointer is a 16-bit register which is always pointing to the next free location in the ...

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ST7LITE49K2 Figure 11. Stack manipulation example CALL Subroutine @ 0180h SP SP PCH @ 01FFh PCL Stack Higher Address = 01FFh Stack Lower Address = 0180h PUSH Y POP Y Interrupt Event ...

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Supply, reset and clock management 7 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external ...

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ST7LITE49K2 1. The DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area in non-volatile memory. They are read-only bytes for the application code. This area cannot be erased or programmed by any ICC operations. For compatibility reasons ...

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Supply, reset and clock management Note: 1 When the internal RC is not selected stopped save power consumption. 2 When the internal RC is selected, the AWU RC is turned on by hardware when entering ...

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ST7LITE49K2 Figure 13. Clock management block diagram CK2 CK1 CR9 CR8 Prescaler CLKSEL[1:0] Option bits CLKIN CLKIN CLKIN CLKIN OSC /OSC1 1-16 MHz or 32 kHz OSC2 f OSC /32 DIVIDER AVDTHCR CK0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 ...

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Supply, reset and clock management 7.2 Multi-oscillator (MO) The main clock of the ST7 can be generated by four different source types coming from the multi-oscillator block ( MHz): ● An external source ● 5 different configurations for ...

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ST7LITE49K2 Table 6. ST7 clock sources 7.3 Reset sequence manager (RSM) 7.3.1 Introduction The reset sequence manager includes three RESET sources as shown in ● External RESET source pulse ● Internal LVD RESET (Low Voltage Detection) ● Internal WATCHDOG RESET ...

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Supply, reset and clock management Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is not programmed. For this reason recommended to keep the RESET pin in low state until ...

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ST7LITE49K2 7.3.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low ...

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Supply, reset and clock management 7.3.5 Internal watchdog reset The Reset sequence generated by an internal watchdog counter overflow is shown in Figure 16: Reset sequences Starting from the watchdog counter underflow, the device RESET pin acts as an output ...

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ST7LITE49K2 7.4 System integrity management (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following the detection ...

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Supply, reset and clock management Figure 17. Low voltage detector vs reset IT+(LVD) V IT-(LVD) RESET Figure 18. Reset and supply management block diagram RESET SEQUENCE RESET 7.4.2 Auxiliary voltage detector (AVD) The ...

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ST7LITE49K2 Note: Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to 196 for more details. Figure 19. Using the AVD to monitor ...

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Supply, reset and clock management 7.5 Register description 7.5.1 Main clock control/status register (MCCSR) Reset value: 0000 0000 (00h Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main Clock Out enable bit This ...

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ST7LITE49K2 7.5.3 System integrity (SI) control/status register (SICSR) Reset value: 011x 0x00 (xxh CR1 Bit 7 = Reserved, must be kept cleared Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits These bits, as well as CR[9:2] bits ...

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Supply, reset and clock management Bit 0 = AVDIE Voltage detector interrupt enable bit This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is ...

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ST7LITE49K2 7.5.5 Clock controller control/status register (CKCNTCSR) Reset value: 0000 1001 (09h Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware ...

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Interrupts 8 Interrupts 8.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – software programmable ...

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ST7LITE49K2 Table 14. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 20. Interrupt processing flowchart RESET RESTORE PC FROM STACK Level Low High PENDING Y ...

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Interrupts 8.2.1 Servicing pending interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: ● The highest software priority interrupt is serviced, ● If several ...

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ST7LITE49K2 Maskable sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and register). ...

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Interrupts 8.4 Concurrent and nested management The following Figure 22 first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure lowest to the highest: MAIN, IT5, IT4, IT3, IT2, IT1, ...

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ST7LITE49K2 8.5 Description of interrupt registers 8.5.1 CPU CC register interrupt bits Reset value: 111x 1010(xAh Bits I1, I0 Software interrupt priority bits These two bits indicate the current interrupt software priority (see These ...

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Interrupts The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, ...

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ST7LITE49K2 Table 18. ST7LITE49K2 interrupt mapping Source Number block RESET TRAP 0 AWU 1 AVD Auxiliary Voltage Detector interrupt 2 COMPA 3 COMPB 4 ei0 External interrupt 0 (Port A) 5 ei1 External interrupt 1 (Port B) 6 ei2 External ...

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Interrupts 8.5.3 External interrupt control register (EICR) Reset value: 0000 0000 (00h Bits 7:6 = Reserved, must be kept cleared. Bits 5:4 = IS2[1:0] ei2 sensitivity bits These bits define the interrupt sensitivity for ei2 (Port C) ...

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ST7LITE49K2 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and Slow-Wait) ● ...

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Power saving modes 9.2 Slow mode This mode has two targets: ● To reduce power consumption by decreasing the internal clock in the device, ● To adapt the internal clock frequency (f Slow mode is controlled by the SMS bit ...

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ST7LITE49K2 Figure 26. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. ...

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Power saving modes 9.4.1 Active-halt mode Active-Halt mode is the lowest power consumption mode of the MCU with a real-time clock available entered by executing the ‘HALT’ instruction when Active-halt mode is enabled. The MCU can exit Active-Halt ...

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ST7LITE49K2 Figure 28. Active-halt mode flowchart 1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite timer RTC ...

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Power saving modes Figure 29. Halt timing overview 1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode. Figure 30. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section ...

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ST7LITE49K2 Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with ...

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Power saving modes As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (f a fixed divider and a programmable prescaler controlled by ...

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ST7LITE49K2 Figure 33. AWUFH mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts ...

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Power saving modes 9.5.1 Register description 9.5.2 AWUFH control/status register (AWUCSR) Reset value: 0000 0000 (00h Bits 7:3 = Reserved Bit 2 = AWUF Auto-wakeup flag This bit is set by hardware when the AWU module generates ...

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ST7LITE49K2 9.5.3 AWUFH prescaler register (AWUPR) Reset value: 1111 1111 (FFh) 7 AWUPR7 AWUPR6 Bits 7:0= AWUPR[7:0] Auto-wakeup prescaler These 8 bits define the AWUPR Dividing factor (see Table 21. Configuring the dividing factor AWUPR[7:0 00h 01h ... FEh FFh ...

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I/O ports 10 I/O ports 10.1 Introduction The I/O ports allow data transfer. An I/O port can contain pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins ...

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ST7LITE49K2 Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector ...

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I/O ports 10.2.3 Alternate functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip be input/output to which ports. A signal coming from an on-chip peripheral can be output ...

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ST7LITE49K2 Table 24. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with Interrupt Output Open Drain (logic level) 1. Off means implemented not activated, On means implemented and activated. Table 25. I/O port configuration PAD PAD PAD ...

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I/O ports 10.2.4 Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected ...

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ST7LITE49K2 10.6 Interrupts The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction). Table 27. Description of interrupt events ...

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I/O ports Table 30. PC3 pin (continued) Table 31. Port configuration Port Pin name Port A Port B Port C Table 32. I/O port register mapping and reset values Address Register 7 label (Hex.) PADR MSB 0000h Reset Value 0 ...

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ST7LITE49K2 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon ...

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On-chip peripherals The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored ...

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ST7LITE49K2 11.1.6 Register description Control register (WDGCR) Reset value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog ...

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On-chip peripherals 11.2 Dual 12-bit autoreload timer 11.2.1 Introduction The 12-bit Autoreload timer can be used for general-purpose timing functions based on one or two free-running 12-bit upcounters with an Input Capture register and four PWM output channels. ...

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ST7LITE49K2 Figure 37. Single timer mode (ENCNTR2=0) ATIC Edge Detection Circuit 12-Bit Autoreload register 1 Clock Control Figure 38. Dual timer mode (ENCNTR2=1) Edge Detection Circuit ATIC 12-Bit Autoreload register 1 12-Bit Autoreload register 2 Control LTIC 12-bit Input Capture ...

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On-chip peripherals 11.2.3 Functional description PWM mode This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins. ● PWM frequency The four PWM signals can have the same frequency (f frequencies. This ...

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ST7LITE49K2 The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. ● Polarity inversion The polarity bits can be used to invert any of the four output ...

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On-chip peripherals Figure 41. PWM signal from 0% to 100% duty cycle f COUNTER COUNTER DCRx=000h DCRx=FFDh DCRx=FFEh DCRx=000h Dead time generation A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for ...

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ST7LITE49K2 Figure 42. Dead time generation CK_CNTR1 CNTR1 PWM 0 PWM 1 PWM 0 PWM 1 In the above example, when the DTE bit is set: ● PWM goes low at DCR0 match and goes high at ATR1+Tdt ● PWM1 ...

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On-chip peripherals When a break function is activated (BAx bit =1 and BREN1/BREN2 =1): ● The break pattern (PWM[3:0] bits in the BREAKCR1) is forced directly on the PWMx output pins if respective OEx is set. (after the inverter). ● ...

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ST7LITE49K2 When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set. In Single ...

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On-chip peripherals Figure 45. Block diagram of input capture mode ATIC ATCSR f LTIMER (1 ms timebase @ 8MHz) f CPU 32 MHz OFF Figure 46. Input capture timing diagram f COUNTER COUNTER1 01h ATIC PIN ICF FLAG Long range ...

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ST7LITE49K2 Figure 47. Long range input capture block diagram ICS LTIC 1 ATIC 0 Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when signal transition occurs, software must mask one interrupt by ...

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On-chip peripherals Now pulse width P between first capture and second capture is given by: P decimal FFF + where N is the number of overflows of 12-bit CNTR1. Figure 48. Long range input capture timing diagram f OSC/32 TB ...

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ST7LITE49K2 One pulse mode One pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in PWM3CSR register is ...

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On-chip peripherals How to enter one pulse mode The steps required to enter One Pulse mode are the following: 1. Load ATR2H/ATR2L with required value. 2. Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3. 3. Set OP3 ...

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ST7LITE49K2 Figure 51. Dynamic DCR2/3 update in one pulse mode f counter2 CNTR2 LTIC FORCE2 TRAN2 DCR2/3 PWM2/3 Force update In order not to wait for the counter programmable counter which when set, make the counters start with the overflow ...

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On-chip peripherals 11.2.4 Low power modes Table 35. Effect of low power modes on autoreload timer Mode Wait Halt 11.2.5 Interrupts Table 36. Description of interrupt events Interrupt event Overflow Event AT4 IC Event Overflow Event2 Note: The AT4 IC ...

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ST7LITE49K2 Bits 4:3 = CK[1:0] Counter clock selection bits These bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. Table 37. Counter clock selection Bit 2 = ...

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On-chip peripherals Bits 11:0 = CNTR1[11:0] Counter value This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 increments continuously as soon as a counter clock is selected. To obtain the 12-bit value, ...

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ST7LITE49K2 PWMX control status register (PWMxCSR) Reset value: 0000 0000 (00h Bits 7:4= Reserved, must be kept cleared. Bit 3 = OP_EN One Pulse Mode Enable bit This bit is read/write by software and cleared by hardware ...

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On-chip peripherals Bit 6 = BR1EDGE Break 1 input edge selection bit This bit is read/write by software and cleared by hardware after reset. It selects the active level of Break 1 signal. 0: Low level of Break 1 selected ...

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ST7LITE49K2 Bit 4 = BP2EN Break 2 pin enable bit This bit is read/write by software and cleared by hardware after Reset. 0: BREAK2 pin disabled 1: BREAK2 pin enabled Bits 3:2 = Reserved, must be kept cleared Bit 1 ...

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On-chip peripherals Input capture register high (ATICRH) Reset value: 0000 0000 (00h Bits 15:12 = Reserved. Input capture register low (ATICRL) Reset value: 0000 0000 (00h) 7 ICR7 ICR6 Bits 11:0 = ICR[11:0] Input Capture Data. This is ...

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ST7LITE49K2 Timer control register 2 (ATCSR2) Reset value: 0000 0011 (03h) 7 FORCE2 FORCE1 Bit 7 = FORCE2 Force counter 2 overflow bit This bit is read/set by software. When set, it loads FFFh in the CNTR2 register ...

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On-chip peripherals Bit 1= TRAN2 Transfer enable2 bit This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It allows the value of the Preload ...

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ST7LITE49K2 Dead time generator register (DTGR) Reset value: 0000 0000 (00h) 7 DTE DT6 Bit 7 = DTE Dead time enable bit This bit is read/write by software. It enables a dead time generation on PWM0/PWM1 Dead time ...

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On-chip peripherals Table 38. Register mapping and reset values (continued) Add. Register 7 (Hex) label DCR0L DCR7 001C Reset Value 0 DCR1H 001D 0 Reset Value DCR1L DCR7 001E Reset Value 0 DCR2H 001F 0 Reset Value DCR2L DCR7 0020 ...

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ST7LITE49K2 11.3 Lite timer 2 (LT2) 11.3.1 Introduction The Lite timer can be used for general-purpose timing functions based on two free- running 8-bit upcounters, a watchdog function and an 8-bit Input Capture register. 11.3.2 Main features ● ...

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On-chip peripherals 11.3.3 Functional description Timebase counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f counter rolls over from F9h ...

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ST7LITE49K2 11.3.4 Low power modes Table 39. Effect of low power modes on Lite timer 2 Mode Slow Wait Active-halt Halt 11.3.5 Interrupts Table 40. Description of interrupt events Interrupt Event Timebase 1 Event Timebase 2 Event IC Event The ...

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On-chip peripherals Bit 0 = TB2F Timebase 2 Interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect Counter 2 overflow 1: A Counter 2 ...

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ST7LITE49K2 Bit 6 = ICF Input capture flag This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value Input Capture 1: An Input ...

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On-chip peripherals Table 41. Lite timer register mapping and reset values Address Register 7 label (Hex.) LTCSR1 ICIE 0F Reset Value 0 LTICR ICR7 10 Reset Value 0 114/245 ICF TB TB1IE TB1F ICR6 ...

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ST7LITE49K2 11.4 16-bit timer 11.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input capture) ...

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On-chip peripherals Counter register (CR) ● Counter high register (CHR) is the most significant byte (MSB). ● Counter low register (CLR) is the least significant byte (LSB). Alternate counter register (ACR) ● Alternate counter high register (ACHR) is the MSB. ...

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ST7LITE49K2 Figure 55. Timer block diagram f CPU 8 high EXEDG 1/2 1/4 1/8 EXTCLK pin CC[1:0] Overflow detect circuit ICF1 OCF1 TOF ICF2 CSR (control/status register ICIE OCIE TOIE FOLV2 (1) Timer interrupt 1. If IC, OC and TO ...

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On-chip peripherals 16-bit read sequence (from either the counter register or the alternate counter register) Figure 56. 16-bit read sequence The user must read the MSB first, then the LSB value is buffered automatically. This buffered value remains unchanged until ...

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ST7LITE49K2 A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 57. ...

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On-chip peripherals Input capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the ...

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ST7LITE49K2 the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6 The TOF bit can be used ...

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On-chip peripherals Output compare In this section, the index, i, may because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a ...

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ST7LITE49K2 The OC R register value required for a specific timing application can be calculated using i the following formula: Equation 1 Where: Δ output compare period (in seconds CPU clock frequency (in hertz) CPU = ...

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On-chip peripherals Forced compare output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is ...

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ST7LITE49K2 Figure 64. Output compare timing diagram, f Output compare register i (OCRi) Output compare flag i (OCFi) One pulse mode One pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via ...

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On-chip peripherals Figure 65. One pulse mode sequence When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1 register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the ...

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ST7LITE49K2 Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an output compare interrupt. 2 When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both ...

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On-chip peripherals Note: There is a locking mechanism for transferring the OCiR value to the buffer. After a write to the OCiHR register, transfer of the new compare value to the buffer is inhibited until OCiLR is also written. Unlike ...

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ST7LITE49K2 The OC R register value required for a specific timing application can be calculated using i the following formula: Equation 5 Where signal or pulse period (in seconds CPU clock frequency (in hertz) CPU = ...

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On-chip peripherals 11.4.5 Interrupts Table 43. 16-bit timer interrupt control/wakeup capability Input capture 1 event/counter reset in PWM mode Input capture 2 event Output compare 1 event (not available in PWM mode) Output compare 2 event (not available in PWM ...

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ST7LITE49K2 11.4.7 16-bit timer registers Each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. ...

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On-chip peripherals Bit 1 = IEDG1 Input edge 1 This bit determines which type of level transition on the ICAP1 pin triggers the capture falling edge triggers the capture 1: A rising edge triggers the capture Bit 0 ...

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ST7LITE49K2 10: Timer clock = f 11: Timer clock = external clock (where available) Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input edge 2 This bit ...

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On-chip peripherals Bit 4 = ICF2 Input capture flag input capture (reset value input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the ...

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ST7LITE49K2 Timer A output compare 1 high register (TAOC1HR) Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB Timer A output compare ...

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On-chip peripherals Counter high register (CHR) Reset value: 1111 1111 (FFh) This is an 8-bit read-only register that contains the high part of the counter value. 7 MSB Counter low register (CLR) Reset value: 1111 1100 (FCh) This is an ...

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ST7LITE49K2 Input capture 2 high register (IC2HR) Reset value: undefined This is an 8-bit read-only register that contains the high part of the counter value (transferred by the input capture 2 event). 7 MSB Input capture 2 low register (IC2LR) ...

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On-chip peripherals Table 45. 16-bit timer register map and reset values (continued) Address (Hex.) Register label TAACHR 5E Reset value TAACLR 5F Reset value TAICHR2 60 Reset value TAICLR2 61 Reset value TAOCHR2 62 Reset value TAOCLR2 63 Reset value ...

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ST7LITE49K2 2 11 bus interface (I 11.5.1 Introduction 2 The I C Bus Interface serves as an interface between the microcontroller and the serial I bus. It provides both multimaster and slave functions, and controls all I sequencing, ...

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On-chip peripherals Mode selection The interface can operate in the four following modes: ● Slave transmitter/receiver ● Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition ...

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ST7LITE49K2 2 When the I C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. 2 When the I C ...

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On-chip peripherals 11.5.4 Functional description Refer to the CR, SR1 and SR2 registers default the I C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the ...

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ST7LITE49K2 Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: EVF and STOPF bits with an interrupt if the ITE bit is set. Then ...

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On-chip peripherals Master mode To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL ...

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ST7LITE49K2 Master transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 ...

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On-chip peripherals Figure 71. Transfer sequencing 7-bit slave receiver S Address A 7-bit slave transmitter S Address A 7-bit master receiver S Address A EV5 7-bit master transmitter S Address A EV5 10-bit slave receiver S Header A 10-bit slave ...

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ST7LITE49K2 subsequent EV4 is not seen. 6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. 7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. 8. EV6: EVF=1, cleared by reading SR1 register followed by writing ...

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On-chip peripherals 11.5.7 Register description control register (I2CCR) Reset value: 0000 0000 (00h Bits 7:6 = Reserved. Forced hardware. Bit Peripheral Enable bit This bit is set and ...

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ST7LITE49K2 Bit 1 = STOP Generation of a Stop condition bit This bit is set and cleared by software also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). ...

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On-chip peripherals status register 1 (I2CSR1) Reset value: 0000 0000 (00h) 7 EVF ADD10 Bit 7 = EVF Event flag This bit is set by hardware as soon as an event occurs cleared by software ...

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ST7LITE49K2 Bit 3 = BTF Byte Transfer Finished bit This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE= cleared by software reading SR1 register followed by ...

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On-chip peripherals status register 2 (I2CSR2) Reset value: 0000 0000 (00h Bits 7:5 = Reserved. Forced hardware. Bit Acknowledge failure bit This bit is set by hardware when ...

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ST7LITE49K2 Note Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication Bit 0 = GCAL General Call ...

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On-chip peripherals own address register (I2COAR1) Reset value: 0000 0000 (00h) 7 ADD7 ADD6 ● In 7-bit addressing mode Bits 7:1 = ADD[7:1] Interface address. These bits define the I interface. They are not cleared when the ...

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ST7LITE49K2 2 Table 49 register mapping and reset values Address Register 7 label (Hex.) I2CCR 0064h Reset 0 Value I2CSR1 EVF 0065h Reset 0 Value I2CSR2 0066h Reset 0 Value I2CCCR FM/SM 0067h Reset 0 Value I2COAR1 ADD7 ...

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On-chip peripherals 11.6 Serial peripheral interface (SPI) 11.6.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which ...

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ST7LITE49K2 Figure 73. Serial peripheral interface block diagram SPIDR Read Buffer MOSI MISO 8-Bit Shift Register SOD bit SCK SS 11.6.4 Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure ...

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On-chip peripherals Figure 74. Single master/ single slave application MASTER MSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage ...

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ST7LITE49K2 Figure 75. Generic SS timing diagram MOSI/MISO Master SS Slave SS (if CPHA = 0) Slave SS (if CPHA = 1) Figure 76. Hardware/software slave select management Master mode operation In master mode, the serial clock is output on ...

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On-chip peripherals Master mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is ...

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ST7LITE49K2 The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see condition (OVR)). 11.6.5 Clock phase and clock polarity Four possible timing ...

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On-chip peripherals Figure 77. Data clock timing diagram SCK (CPOL = 1) SCK (CPOL = 0) MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE SCK (CPOL = 1) SCK (CPOL = 0) MISO MSBit (from ...

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ST7LITE49K2 1. A read access to the SPICSR register while the MODF bit is set write to the SPICR register. Note: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high ...

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On-chip peripherals Figure 78. Clearing the WCOL bit (write collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) Read SPICSR 1st Step 2nd Step Read SPIDR Clearing sequence before SPIF = 1 (during ...

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ST7LITE49K2 Figure 79. Single master / multiple slave configuration SCK MOSI MOSI SCK 5V SS 11.6.7 Low power modes Table 50. Low power mode descriptions Mode Wait Halt 11.6.8 Interrupts Table 51. Interrupt events Interrupt event SPI End of Transfer ...

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On-chip peripherals 11.6.9 Register description SPI control register (SPICR) Reset value: 0000 xxxx (0xh) 7 SPIE SPE Bit 7 = SPIE Serial Peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI ...

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ST7LITE49K2 Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. The slave must have ...

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On-chip peripherals SPI control/status register (SPICSR) Reset Value: 0000 0000 (00h) 7 SPIF WCOL Bit 7 = SPIF Serial peripheral data transfer flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is ...

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ST7LITE49K2 Bit 1 = SSM SS management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section Slave select management. 0: ...

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On-chip peripherals Table 53. SPI register map and reset values Address Register label (Hex.) SPIDR 70 Reset Value SPICR 71 Reset Value SPICSR 72 Reset Value 170/245 MSB SPIE SPE SPR2 MSTR ...

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ST7LITE49K2 11.7 10-bit A/D converter (ADC) 11.7.1 Introduction The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to ...

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On-chip peripherals Figure 80. ST7LITE49K2 ADC block diagram f CPU AIN0 AIN1 AINx Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input ...

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ST7LITE49K2 Configuring the A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt (see I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read as a ...

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On-chip peripherals 11.7.6 Register description Control/status register (ADCCSR) Reset value: 0000 0000 (00h) 7 EOC SPEED Read only Bit 7 = EOC End of conversion bit This bit is set by hardware cleared by hardware when software reads ...

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ST7LITE49K2 Data register high (ADCDRH) Reset value: xxxx xxxx (xxh Bits 7:0 = D[9:2] MSB of Analog Converted Value ADC control/data register low (ADCDRL) Reset value: 0000 00xx (0xh Bits 7:5 = Reserved. Forced ...

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On-chip peripherals Table 57. ADC register mapping and reset values Address Register label (Hex.) ADCCSR 0036h Reset Value ADCDRH 0037h Reset Value ADCDRL 0038h Reset Value 176/245 EOC SPEED ADON ...

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ST7LITE49K2 11.8 Analog comparator (CMP) 11.8.1 Introduction The CMP block consists of two analog comparators (CMPA and CMPB) and an internal voltage reference. The voltage reference can be external or internal, selectable under program control. The comparator input pins COMPIN+ ...

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On-chip peripherals 11.8.3 Functional description To make an analog comparison, the CMPON bit in the CMPxCR register must be set to power-on the comparator and internal voltage reference module. The VP comparator A input is mapped on PC6 and the ...

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ST7LITE49K2 Figure 82. Analog comparator Comparator + - CHYST CMPxCR 11.8.4 Register description Internal voltage reference register (VREFCR) Reset Value: 0000 0000 (00h) 7 VCEXT VCBGR Bit 7 = VCEXT External voltage reference for comparators This bit is set or ...

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On-chip peripherals Table 59. Voltage reference programming VCEXT bit Bit 1 = VCEXTB External voltage reference for comparator B Set and cleared ...

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ST7LITE49K2 Comparator control register (CMPxCR) Reset Value: 1000 0000 (80h) 7 CHYST Bit 7 = CHYST Comparator hysteresis enable This bit is set or cleared by software and set by hardware reset. When this bit is set, the comparator hysteresis ...

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On-chip peripherals Note: This bit should be set to enable interrupt only after the comparator has been switched ON, i.e. when CMPON is set. Once CMPON bit is set recommended to wait the specified stabilization time before setting ...

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ST7LITE49K2 12 Instruction set 12.1 ST7 addressing modes The ST7 core features 17 different addressing modes which can be classified in seven main groups: Table 61. Description of addressing modes Addressing mode The ST7 instruction set is designed to minimize ...

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Instruction set Table 62. ST7 addressing mode overview (continued) Mode Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative 1. At the time the instruction is executed, the Program Counter (PC) points ...

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ST7LITE49K2 Table 63. Instructions supporting inherent addressing mode (continued) SLL, SRL, SRA, RLC, RRC 12.1.2 Immediate mode Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Imm Table 64. Instructions supporting ...

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Instruction set Indexed mode (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect modes (short, long) The required data byte to do the operation is found by its ...

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ST7LITE49K2 Table 65. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued) Short instructions only SLL, SRL, SRA, RLC, RRC 12.1.7 Relative modes (direct, indirect) This addressing mode is used to modify the PC register value by adding ...

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Instruction set 12.2 Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 67. ST7 instruction set Load and Transfer ...

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ST7LITE49K2 12.2.1 Illegal opcode reset In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented: a reset is generated if the code to be executed does not correspond to any ...

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Instruction set Table 68. Illegal opcode detection (continued) Mnemo Description JRPL Jump (plus) JREQ Jump (equal) JRNE Jump (not equal) JRC Jump JRNC Jump ...

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ST7LITE49K2 Table 68. Illegal opcode detection (continued) Mnemo Description WFI Wait for Interrupt XOR Exclusive OR Function/Example Dst XOR M A Instruction set Src 191/245 C ...

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Electrical characteristics 13 Electrical characteristics 13.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 13.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

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ST7LITE49K2 Figure 84. Pin input voltage 13.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions ...

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Electrical characteristics Table 70. Current characteristics Symbol I VDD I VSS I IO (2)(3) I INJ(PIN) ΣI (2) INJ(PIN) 1. All power (V ) and ground ( must never be exceeded. This is implicitly insured if V ...

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ST7LITE49K2 13.3 Operating conditions 13.3.1 General operating conditions T = -40 to +125 °C unless otherwise specified. A Table 72. General operating conditions Symbol CPU clock frequency CPU Figure 85. f CPU f CPU FUNCTIONALITY NOT GUARANTEED ...

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Electrical characteristics 13.3.3 Auxiliary voltage detector (AVD) thresholds T = -40 to 125 °C unless otherwise specified A , Table 74. Operating characteristics with AVD Symbol 1=>0 AVDF flag toggle V IT+ (AVD) threshold (V 0=>1 AVDF flag toggle V ...

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ST7LITE49K2 13.3.5 Internal RC oscillator To improve clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100 nF, between the V device Internal RC oscillator calibrated at 5.0 V The ST7 internal clock can be ...

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Electrical characteristics Internal RC oscillator calibrated at 3.3 V The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte). Table 77. Internal RC oscillator characteristics (3.3 V calibration) Symbol Parameter Internal RC oscillator f ...

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ST7LITE49K2 Figure 87. Frequency vs voltage at four different ambient temperatures (RC at 3.3 V) Figure 88. Accuracy voltage at 4 different ambient temperatures ( Figure 89. Accuracy voltage at 4 ...

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Electrical characteristics 13.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values ...