ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 68

• Manufacturer Part Number: ST7FLITE49K2T6
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power saving modes
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Figure 29. Halt timing overview
1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode.
Figure 30. Halt mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
Table 18: ST7LITE49K2 interrupt
during the interrupt routine and cleared when the CC register is popped.
[Active-halt disabled]
INSTRUCTION
RUN
N
HALT INSTRUCTION
WATCHDOG
(Active-halt disabled)
WDGHALT
HALT
mappingfor more details.
RESET
1
INTERRUPT
HALT
Y
1)
256 CPU CYCLE
ENABLE
3)
INTERRUPT
RESET
OR SERVICE INTERRUPT
0
256 CPU CLOCK CYCLE
FETCH RESET VECTOR
DELAY
OR
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BITS
N
DELAY
RESET
Y
WATCHDOG
VECTOR
FETCH
5)
DISABLE
2)
RUN
OFF
OFF
OFF
OFF
ON
ON
X
ON
ON
ON
X
0
4)
4)
ST7LITE49K2