ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 93

• Manufacturer Part Number: ST7FLITE49K2T6
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
Figure 47. Long range input capture block diagram
Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when
signal transition occurs, software must mask one interrupt by clearing the corresponding
ICIE bit before setting the ICS bit.
If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the
Input Capture signal because of different values on LTIC and ATIC. To avoid this situation, it
is recommended to do as follows:
1.
2.
3.
4.
Computing a pulse length in long Input Capture mode is not straightforward since both
timers are used. The following steps are required:
1.
2.
First, reset both ICIE bits.
Then set the ICS bit.
Reset both ICF bits.
And then set the ICIE bit of desired interrupt.
At the first Input Capture on the rising edge of the pulse, we assume that values in the
registers are the following:
–
–
–
–
At the second Input Capture on the falling edge of the pulse, we assume that the values
in the registers are as follows:
–
–
–
–
ATIC
LTIC
LTICR = LT1
ATICRH = ATH1
ATICRL = ATL1
Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to
LTICR = LT2
ATICRH = ATH2
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2.
ICS
1
0
32 MHz
f
LTIMER
OFF
f
cpu
f
OSC/32
LTICR
CNTR1
ATR1
ATICR
12-bit Input Capture register
8-bit Input Capture register
12-bit AutoReload register
8-bit Timebase Counter1
12-bit Upcounter1
12-Bit ARTIMER
LITE TIMER
Figure 48 on page
8 LSB bits
12 MSB bits
On-chip peripherals
94.
20
cascaded
bits
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