ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 105

• Manufacturer Part Number: ST7FLITE49K2T6
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
Note:
Note:
Note:
Timer control register 2 (ATCSR2)
Reset value: 0000 0011 (03h)
Bit 7 = FORCE2 Force counter 2 overflow bit
This bit must not be reset by software
Bit 6 = FORCE1 Force counter 1 overflow bit
This bit must not be reset by software
Bit 5 = ICS Input capture shorted bit
Bit 4 = OVFIE2 Overflow interrupt 2 enable bit
Bit 3 = OVF2 Overflow flag
Bit 2 = ENCNTR2 Enable counter2 for PWM2/3
Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the
counter will restart from the last value.
FORCE2
This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is
reset by hardware one CPU clock cycle after counter 2 overflow has occurred.
0 : No effect on CNTR2
1 : Loads FFFh in CNTR2
This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset
by hardware one CPU clock cycle after counter 1 overflow has occurred.
0 : No effect on CNTR1
1 : Loads FFFh in CNTR1
This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for
long Input Capture.
0 : ATIC for CNTR1 Input Capture
1 : LTIC for CNTR1 Input Capture
This bit is read/write by software and controls the overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
This bit is set by hardware and cleared by software by reading the ATCSR2 register. It
indicates the transition of the counter2 from FFFh to ATR2 value.
0: No counter overflow occurred
1: Counter overflow occurred
This bit is read/write by software and switches the PWM2/3 operation to the CNTR2
counter. If this bit is set, PWM2/3 will be generated using CNTR2.
0: PWM2/3 is generated using CNTR1.
1: PWM2/3 is generated using CNTR2.
7
FORCE1
ICS
OVFIE2
Read/write
OVF2
ENCNTR2
On-chip peripherals
TRAN2
TRAN1
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