ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 82

• Manufacturer Part Number: ST7FLITE49K2T6
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

On-chip peripherals
11.1.4
11.1.5
82/245
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is free-running: it counts down even if
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see
●
●
●
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Table 33.
1. The timing variation shown in
2. The number of CPU clock cycles applied during the Reset phase (256 or 4096) must be taken into account
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the option byte description in
Using Halt mode with the WDG (WDGHALT option)
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Same behavior in active-halt mode.
Interrupts
None.
CR register.
in addition to these timings.
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
counter code
Watchdog timing
WDG
Table 33: Watchdog
C0h
FFh
Table 33
(1)(2)
timing):
is due to the unknown status of the prescaler when writing to the
Section 14 on page
f
CPU
= 8 MHz
[ms]
min
127
1
230.
[ms]
max
128
2
ST7LITE49K2