ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 13

• Manufacturer Part Number: ST7FLITE49K2T6
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
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Figure 100. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Block diagram of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
One pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Dynamic DCR2/3 update in one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Output compare timing diagram, f
Output compare timing diagram, f
One pulse mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I
I
Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 164
Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
ST7LITE49K2 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Analog comparator and internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . 195
Frequency vs voltage at four different ambient temperatures (RC at 5 V) . . . . . . . . . . . . 198
Frequency vs voltage at four different ambient temperatures (RC at 3.3 V). . . . . . . . . . . 199
Accuracy in % vs voltage at 4 different ambient temperatures (RC at 5 V) . . . . . . . . . . . 199
Accuracy in % vs voltage at 4 different ambient temperatures (RC at 3.3V) . . . . . . . . . . 199
Typical IDD in Run vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Typical IDD in WFI vs. fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Typical IDD in Slow mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Typical IDD in Slow-wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Typical IDD vs. temperature at VDD = 5 V and fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . 202
SPI slave timing diagram with CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
SPI slave timing diagram with CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 210
2
2
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
TIMER
TIMER
= f
= f
CPU
CPU
/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
List of figures
13/245