C8051F352-GQR Silicon Laboratories Inc, C8051F352-GQR Datasheet - Page 187

• Manufacturer Part Number: C8051F352-GQR
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Core: 8051
• Processor Series: C8051F3x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 768 B
• Data Rom Size: 128 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 17
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 8
• Height: 1.4 mm
• Interface Type: I2C, SMBus, SPI, UART
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

*Note: See Table 21.1 for timing parameters.
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SPIBSY
Bit7
R
SPIBSY: SPI Busy (read only).
This bit is set to logic 1 when a SPI transfer is in progress (Master or Slave Mode).
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
SLVSEL: Slave Selected Flag (read only).
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the
instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.
NSSIN: NSS Instantaneous Pin Input (read only).
This bit mimics the instantaneous value that is present on the NSS port pin at the time that
the register is read. This input is not de-glitched.
SRMT: Shift Register Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift register,
and there is no new information available to read from the transmit buffer or write to the
receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from
the transmit buffer or by a transition on SCK.
NOTE: SRMT = 1 when in Master Mode.
RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when the receive buffer has been read and contains no new
information. If there is new information available in the receive buffer that has not been read,
this bit will return to logic 0.
NOTE: RXBMT = 1 when in Master Mode.
MSTEN
R/W
Bit6
SFR Definition 21.1. SPI0CFG: SPI0 Configuration
CKPHA
R/W
Bit5
CKPOL
R/W
Bit4
SLVSEL
Rev. 1.1
Bit3
R
NSSIN
Bit2
R
C8051F350/1/2/3
SRMT
Bit1
R
SFR Address: 0xA1
RXBMT
Bit0
R
Reset Value
00000111
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