C8051F352-GQR Silicon Laboratories Inc, C8051F352-GQR Datasheet - Page 43

• Manufacturer Part Number: C8051F352-GQR
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Core: 8051
• Processor Series: C8051F3x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 768 B
• Data Rom Size: 128 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 17
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 8
• Height: 1.4 mm
• Interface Type: I2C, SMBus, SPI, UART
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.1.3. Modulator Clock
The ADC0CLK register (SFR Definition 5.4) holds the Modulator Clock (MDCLK) divisor value. The modu-
lator clock determines the switching frequency for the ADC sampling capacitors. Optimal performance will
be achieved when the MDCLK frequency is equal to 2.4576 MHz. The modulator samples the input at a
rate of MDCLK / 128.
5.1.4. Decimation Ratio
The decimation ratio of the ADC filters is selected by the DECI[10:0] bits in the ADC0DECH and
ADC0DECL registers (SFR Definition 5.5 and SFR Definition 5.6, respectively). The decimation ratio is
equal to 1 + DECI[10:0]. The decimation ratio determines how many modulator samples are used to gen-
erate a single output word. The ADC output word rate is equal to the modulator sampling rate divided by
the decimation ratio. For more information on how the ADC output word rate is derived, see SFR Definition
5.4 and SFR Definition 5.6. Higher decimation ratios will produce lower-noise results over a longer conver-
sion period. The minimum decimation ratio is 20. When using the fast filter output, the decimation ratio
must be set to a multiple of 8.
Channel
Channel
AIN+
AIN-
Figure 5.2. ADC0 Buffer Control
Bypass Buffer
Bypass Buffer
High Buffer+
Low Buffer+
High Buffer-
Low Buffer-
Rev. 1.1
AD0BPHE
AD0BNHE
AD0BNLE
AD0BNS1
AD0BNS0
AD0BPLE
AD0BPS1
AD0BPS0
To PGA
To PGA
C8051F350/1/2/3
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