C8051F352-GQR Silicon Laboratories Inc, C8051F352-GQR Datasheet - Page 31

• Manufacturer Part Number: C8051F352-GQR
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Core: 8051
• Processor Series: C8051F3x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 768 B
• Data Rom Size: 128 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 17
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 8
• Height: 1.4 mm
• Interface Type: I2C, SMBus, SPI, UART
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.
DGND
XTAL1
XTAL2
AGND
Pinout and Package Definitions
Name
C2CK
P2.0/
P0.2/
P0.3/
/RST
P0.0
P0.1
P0.4
P0.5
C2D
V
AV+
DD
Pin Numbers
‘F350
‘F352
21
22
10
12
11
13
14
15
16
17
18
Table 4.1. Pin Definitions for the C8051F350/1/2/3
9
‘F351
‘F353
17
18
10
11
12
13
14
6
5
8
7
9
D I/O or
D I/O or
D I/O or
A I/O or
D I/O or
D I/O or
Ground Digital Ground. Must be tied to Ground.
Ground Analog Ground. Must be tied to Ground.
Power
Power
D I/O
D I/O
D I/O
D I/O
D I/O
Type
A In
A In
A In
A In
D In
A In
A In
Description
Digital Supply Voltage. Must be tied to +2.7 V to +3.6 V
power.
Analog Supply Voltage. Must be tied to +2.7 V to +3.6 V
power.
Device Reset. Open-drain output of internal POR or V
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1kΩ pull-up to V
recommended. See Reset Sources Section.
Clock signal for the C2 Debug Interface.
Port 2.0. See Port I/O Section for a complete description.
Bi-directional data signal for the C2 Debug Interface.
Port 0.0. See Port I/O Section for a complete description.
Port 0.1. See Port I/O Section for a complete description.
Port 0.2. See Port I/O Section for a complete description.
This pin is the external oscillator return for a crystal or reso-
nator. See Oscillator Section.
Port 0.3. See Port I/O Section for a complete description.
This pin is the excitation driver for an external crystal or res-
onator, or an external clock input for CMOS, capacitor, or
RC oscillator configurations. See Oscillator Section.
Port 0.4. See Port I/O Section for a complete description.
Port 0.5. See Port I/O Section for a complete description.
Rev. 1.1
C8051F350/1/2/3
DD
DD
is
31