HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 14

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.7.00 Oct. 10, 2008 Page xii of lxxxiv
REJ09B0366-0700
Item
5.6.1 Resets
(3) H-UDI Reset
(4) Instruction TLB
Multiple-Hit Exception
(5) Operand TLB
Multiple-Hit Exception
5.6.2 General
Exceptions
(11) General FPU
Disable Exception
5.6.3 Interrupts
(3) Peripheral Module
Interrupts
Page
161
162
163
174
180
Revision (See Manual for Details)
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
...
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
...
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
...
SR.IMASK = B'1111;
Note amended
Note: * FPU instructions are instructions in which the first 4 bits
Description amended
INTEVT = H'00000400 ~ H'00000B80;
of the instruction code are H'F (but excluding undefined
instruction H'FFFD), and the LDS, STS, LDS.L, and
STS.L instructions corresponding to FPUL and FPSCR.