HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 942

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 20 User Break Controller (UBC)
20.2.3
Legend: *: Undefined
Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID
used in the channel A break conditions. BASRA is not initialized by a power-on reset or manual
reset.
Bits 7 to 0—Break ASID A7 to A0 (BASA7–BASA0): These bits hold the ASID (bits 7–0) used
in the channel A break conditions.
20.2.4
Legend: *: Undefined
Break address mask register A (BAMRA) is an 8-bit readable/writable register that specifies
which bits are to be masked in the break ASID set in BASRA and the break address set in BARA.
BAMRA is not initialized by a power-on reset or manual reset.
Bits 7 to 4—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Break ASID Mask A (BASMA): Specifies whether all bits of the channel A break ASID7
to ASID0 (BASA7–BASA0) are to be masked.
Bit 2: BASMA
0
1
Rev.7.00 Oct. 10, 2008 Page 856 of 1074
REJ09B0366-0700
Initial value:
Initial value:
Break ASID Register A (BASRA)
Break Address Mask Register A (BAMRA)
R/W:
R/W:
Bit:
Bit:
BASA7
Description
All BASRA bits are included in break conditions
No BASRA bits are included in break conditions
R/W
—
R
7
7
0
*
BASA6
R/W
—
R
6
6
*
0
BASA5
R/W
—
R
5
5
0
*
BASA4
R/W
—
R
4
*
4
0
BAMA2 BASMA BAMA1 BAMA0
BASA3
R/W
R/W
3
3
*
*
BASA2
R/W
R/W
2
2
*
*
BASA1
R/W
R/W
1
*
1
*
BASA0
R/W
R/W
0
0
*
*