HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 720

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
11. Clearing DDT mode
12. Confirming DMA transfer requests and number of transfers executed
14.6
14.6.1
Figure 14.53 is a block diagram of the DMAC in the SH7750R.
Rev.7.00 Oct. 10, 2008 Page 634 of 1074
REJ09B0366-0700
Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT
bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode,
the DMAC will freeze.
This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT
mode.
The channel associated with a DMA bus cycle being executed in response to a DMA transfer
request can be confirmed by determining the level of external pins ID1 and ID0 at the rising
edge of the CKIO clock while TDACK is asserted.
(ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3)
Configuration of the DMAC (SH7750R)
Block Diagram of the DMAC