HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 788

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for
multiprocessor serial reception.
Use the following procedure for multiprocessor serial data reception after enabling the SCI for
reception.
1. Method for determining whether an interrupt generated during receive operation is a
Rev.7.00 Oct. 10, 2008 Page 702 of 1074
REJ09B0366-0700
Serial
data
TDRE
TEND
multiprocessor interrupt
When an interrupt such as RXI occurs during receive operation using the on-chip SCI
multiprocessor communication function, check the state of the MPIE bit in the SCSCR1
register as part of the interrupt handling routine.
a. If the MPIE bit in the SCSCR1 register is set to 1
1
Ignore the received data.
Data with the multiprocessor bit (MPB) set to 0 and intended for another station was
received, and the RDRF bit in the SCSCR1 register was set to 1. Therefore, clear the
RDRF bit in the SCSCR1 register to 0.
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Start
bit
0
D0 D1
One frame
Data
D7
Multi-
proces-
sor bit
MPBT bit cleared to 0, data
written to SCTDR1, and
TDRE flag cleared to 0 by
TEI interrupt handler
1
Multiprocessor Bit, One Stop Bit)
Stop
bit
1
Data written to SCTDR1
and TDRE flag cleared
to 0 by TXI interrupt
handler
Start
bit
0
D0 D1
Data
D7
Multi-
proces-
sor bit
0
Stop
bit
TXI interrupt
request
1
Start
bit
0
D0 D1
Data
D7
Multi-
proces-
sor bit
TEI interrupt
request
0
Stop
bit
Idle state
(mark state)
1