HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 541

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only
while the CAS signal is asserted in a data read cycle, an EDO (extended data out) mode is also
provided in which, once the CAS signal is asserted while the RAS signal is asserted, even if the
CAS signal is negated, data is output to the data bus until the CAS signal is next asserted. In this
LSI, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst access using fast
page mode, or EDO mode normal access/burst access, to be selected for DRAM. When EDO
mode is set, BE must be set to 1 in MCR. EDO mode normal access is shown in figure 13.20, and
burst access in figure 13.21.
CAS Negation Period: The CAS negation period can be set to 1 or 2 by means of the TCAS bit in
the MCR register.
Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)
CKIO
A25–A0
CSn
RD/WR
RAS
CASn
D63–D0
(read)
BS
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Tr1
Row
Tr2
Tc1
Column
Tc2
Rev.7.00 Oct. 10, 2008 Page 455 of 1074
Section 13 Bus State Controller (BSC)
Tce
Tpc
REJ09B0366-0700