HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 446

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
13.1.3
Table 13.1 shows the BSC pin configuration.
Table 13.1 BSC Pins
Name
Address bus
Data bus
Data bus/port
Bus cycle start
Chip select 6−0
Read/write
Row address
strobe
Read/column
address strobe/
cycle frame
Rev.7.00 Oct. 10, 2008 Page 360 of 1074
REJ09B0366-0700
Pin Configuration
Signals
A25−A0
D63−D52,
D31−D0
D51−D32/
PORT19−
PORT0
BS
CS6−CS0
RD/WR
RAS
RD/CASS/
FRAME
I/O
O
I/O
I/O
O
O
O
O
O
Address output
Data input/output
When port functions are not used: data input/output
Signal that indicates the start of a bus cycle
Chip select signals that indicate the area being
Data bus input/output direction designation signal
Strobe signal that indicates a read cycle
Description
When port functions are used and DDT mode is
selected, input the DTR format. Otherwise, when
port functions are used, D63−D52 cannot be used
and should be left open.
When port functions are used: input/output port
(input or output set for each bit by register)
When setting synchronous DRAM interface:
asserted once for a burst transfer
For other burst transfers: asserted each data cycle
accessed
CS5 and CS6 are also used as PCMCIA CE1A and
CE1B
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
RAS signal when setting DRAM/synchronous DRAM
interface
When setting synchronous DRAM interface: CAS
signal
When setting MPX interface: FRAME signal