HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 25

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
13.3.8 MPX Interface
Figure 13.68 MPX
Interface Timing 11
(Burst Write Cycle, AnW
= 0, No External Wait,
Bus Width: 32 Bits,
Transfer Data Size: 64
Bits)
Figure 13.69 MPX
Interface Timing 12
(Burst Write Cycle, AnW
= 1, One External Wait
Inserted, Bus Width: 32
Bits, Transfer Data Size:
64 Bits)
13.3.16 Notes on
Usage
Synchronous DRAM
Mode Register Setting
(SH7750, SH7750S
Only):
BSREQ Output in
Partial-Sharing Master
Mode
14.2.1 DMA Source
Address Registers 0–3
(SAR0–SAR3)
14.2.4 DMA Channel
Control Registers 0−3
(CHCR0−CHCR3)
Bits 13 and 12⎯Source
Address Mode 1 and 0
(SM1, SM0):
Page
523
524
543
543, 544 Newly added
552
560
Revision (See Manual for Details)
Title amended
Title amended
Notes amended
3. If synchronous DRAM mode register setting is performed
immediately following write access to the on-chip peripheral
modules*
cannot be guaranteed. Note that following power-on,
synchronous DRAM mode register settings should be
performed before accessing synchronous DRAM. After making
mode register settings, do not change them.
Description deleted
When transfer is performed from memory to an external device
with DACK in DDT mode, DTR format [31:0] is set in SAR0
[31:0]. For details, see Data Transfer Request Format in section
14.5.2, Pin in DDT Mode.
Description amended
These bits specify incrementing/decrementing of the DMA
transfer source address. The specification of these bits is
ignored when data is transferred from an external device to
external memory in single address mode. For channel 0, in
DDT mode these bits are set to SM1 = 0 and SM0 = 1 with the
DTR format.
2
, the values written to the on-chip peripheral modules
Rev.7.00 Oct. 10, 2008 Page xxiii of lxxxiv
REJ09B0366-0700