HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 686

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding
channel when either of the following conditions is satisfied:
• The value in the DMA transfer count register (DMATCR) reaches 0.
• The DE bit in the DMA channel control register (CHCR) is cleared to 0.
1. End of transfer when DMATCR = 0
2. End of transfer when DE = 0 in CHCR
Conditions for Ending Transfer Simultaneously on All Channels: Transfer ends on all
channels simultaneously when either of the following conditions is satisfied:
• The address error bit (AE) or NMI flag (NMIF) in the DMA operation register (DMAOR) is
• The DMA master enable bit (DME) in DMAOR is cleared to 0.
1. End of transfer when AE = 1 in DMAOR
Rev.7.00 Oct. 10, 2008 Page 600 of 1074
REJ09B0366-0700
When the DMATCR value reaches 0, DMA transfer ends on the corresponding channel and
the transfer end flag (TE) in CHCR is set. If the interrupt enable bit (IE) is set at this time, an
interrupt (DMTE) request is sent to the CPU.
Transfer ending when DMATCR = 0 does not follow the procedures described in 1 to 4 in
section 14.3.6, Ending DMA Transfer.
When the DMA enable bit (DE) in CHCR is cleared, DMA transfer is suspended on the
corresponding channel. The TE bit is not set in this case. Transfer ending in this case follows
the procedures described in 1 to 4 in section 14.3.6, Ending DMA Transfer.
set to 1.
If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on all
channels in accordance with the conditions in 1 to 4 in section 14.3.6, Ending DMA Transfer,
and the bus is passed to the CPU. Therefore, when AE is set to 1, the values in the DMA
source address register (SAR), DMA destination address register (DAR), and DMA transfer
count register (DMATCR) indicate the addresses for the DMA transfer to be performed next
and the remaining number of transfers. The TE bit is not set in this case. Before resuming
transfer, it is necessary to make a new setting for the channel that caused the address error,
then write 0 to the AE bit after first reading 1 from it. Acceptance of external requests is
suspended while AE is set to 1, so a DMA transfer request must be reissued when resuming
transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the
DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to
0 before the new setting is made.