HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 730

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source.
For details of the settings, see the description of the RS3−RS0 bits in section 14.2.4, DMA
Channel Control Registers 0−3 (CHCR0−CHCR3).
Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. For details of the settings, see
the description of the TM bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size (access
size). For details of the settings, see the description of the TS2−TS0 bits in section 14.2.4, DMA
Channel Control Registers 0−3 (CHCR0−CHCR3).
Bit 3⎯Request Queue Clear (QCL): Writing a 1 to this bit clears the request queues of the
corresponding channel as well as any external requests that have already been accepted. This bit is
only functional when DMAOR.DDT = 1 and DMAOR.DBL = 1.
CHCR Bit 3
QCL
0
1
Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated
after the number of data transfers specified in DMATCR (when TE = 1). For details of the
settings, see the description of the IE bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in
DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or
clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1,
the transfer enabled state is not entered even if the DE bit is set to 1. For details of the settings, see
the description of the TE bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
Rev.7.00 Oct. 10, 2008 Page 644 of 1074
REJ09B0366-0700
Description
This bit is always read as 0.
Writing a 0 to this bit is invalid.
When DMAOR.DBL = 1, writing a 1 to this bit clears the request queues on the
DDT side and any external requests stored in the DMAC. The written value is
not retained.
(Initial value)