HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 494

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Section 13 Bus State Controller (BSC)
Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is
performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh
request cycle generation timer can be used as an interval timer.
Bit 2: RFSH
0
1
Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is
performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS-
before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using
the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is
issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When
the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous
DRAM, after waiting for the end of any currently executing external bus cycle. All refresh
requests for memory in the self-refresh state are ignored.
Bit 1: RMODE
0
1
Bit 0—EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when
using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of
memory other than DRAM. Set this bit to 1 only when DRAM is used.
Rev.7.00 Oct. 10, 2008 Page 408 of 1074
REJ09B0366-0700
Description
Refreshing is not performed
Refreshing is performed
Description
CAS-before-RAS refreshing is performed (when RFSH = 1)
Self-refreshing is performed (when RFSH = 1)
(Initial value)
(Initial value)

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