UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 135

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Notes 1.
Address Special Function Register (SFR) Name
FFE8H
FFE9H
FFEAH
FFEBH
FFF0H
FFF3H
FFF4H
FFFBH
2.
3.
4.
Priority specification flag register 0L
Priority specification flag register 0H
Priority specification flag register 1L
Priority specification flag register 1H
Internal memory size switching
register
Memory bank select register
Internal expansion RAM size switching
register
Processor clock control register
This register is incorporated only in products whose flash memory is at least 96 KB.
Set this register only in products with internal expansion RAM.
Regardless of the internal memory capacity, the initial values of the internal memory size switching register
(IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/Kx2
microcontrollers are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product
as indicated in Tables 3-1 and 3-2.
The ROM and RAM capacities of the products with the on-chip debug function can be debugged by setting
IMS and IXS, according to the debug target products. Set IMS and IXS according to the debug target
products.
Notes 3,4
Notes 3,4
Table 3-8. Special Function Register List (5/5)
PR0
PR1
IMS
BANK
IXS
PCC
Symbol
PR0L
PR0H R/W
PR1L
PR1H R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Manipulatable Bit Unit
1 Bit
√
√
√
√
−
−
−
√
8 Bits 16 Bits
√
√
√
√
√
√
√
√
CHAPTER 3 CPU ARCHITECTURE
√
√
−
−
−
−
Reset
After
CFH
FFH
FFH
FFH
FFH
0CH
00H
01H
Note
K
B
2
2
√
√
√
√
√
−
√
Note
K
C
2
2
√
√
√
√
√
−
√
Note 1 Note 1 Note 1
Note
D
2
K
2
√
√
√
√
√
√
Note
K
E
2
2
√
√
√
√
√
√
K
F
2
√
√
√
√
√
√
√
135