UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 451
UPD78F0513AGA-GAM-AX
Manufacturer Part Number
UPD78F0513AGA-GAM-AX
Description
MCU 8BIT 48-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGA-GAM-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGA-GAM-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD78F0513AGA-GAM-AX
Manufacturer:
NEC
Quantity:
20 000
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78K0/Kx2
(4) Permissible baud rate range during reception
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by using
As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate generator
control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the
data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)
Maximum permissible
Minimum permissible
Brate: Baud rate of UART0
k:
FL:
Margin of latch timing: 2 clocks
Data frame length
data frame length
data frame length
the calculation expression shown below.
Set value of BRGC0
1-bit data length
of UART0
−
1
Figure 14-12. Permissible Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
Bit 0
Bit 0
FL
Bit 0
Bit 1
Bit 1
Bit 1
1 data frame (11
FLmin
CHAPTER 14 SERIAL INTERFACE UART0
FLmax
Bit 7
Bit 7
FL)
Bit 7
Parity bit
Parity bit
Parity bit
Stop bit
Stop bit
Stop bit
451
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