UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 401

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
11.4.3 Setting window open period of watchdog timer
(0080H). The outline of the window is as follows.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again.
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal reset
Example: If the window open period is 25%
Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
The window open period to be set is as follows.
Counting
starts
signal is generated.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
overflow time regardless of the timing of the writing, and the watchdog timer starts counting again.
WINDOW1
Internal reset signal is generated
if ACH is written to WDTE.
1
0
0
1
Window close period (75%)
2. Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer at 1.8 V
3. The watchdog timer continues its operation during self-programming and EEPROM
prohibited.
≤ V
emulation of the flash memory. During processing, the interrupt acknowledge time is
delayed. Set the overflow time and window size taking this delay into consideration.
Table 11-4. Setting Window Open Period of Watchdog Timer
WINDOW0
DD
< 2.7 V.
0
1
0
1
25%
50%
75%
100%
Window Open Period of Watchdog Timer
Counting starts again when
ACH is written to WDTE.
Window open
period (25%)
Overflow
time
CHAPTER 11 WATCHDOG TIMER
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