UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 960

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Serial
interface
UART6
Function
ASIM6:
Asynchronous
serial interface
operation mode
register 6
ASIS6:
Asynchronous
serial interface
reception error
status register 6
ASIF6:
Asynchronous
serial interface
transmission
status register 6
CKSR6: Clock
selection register
6
BRGC6: Baud
rate generator
control register 6 The baud rate is the output clock of the 8-bit counter divided by 2.
ASICL6:
Asynchronous
serial interface
control register 6
Details of
Function
To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the
transmission, clear TXE6 to 0, and then clear POWER6 to 0.
To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the
reception, clear RXE6 to 0, and then clear POWER6 to 0.
Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the R
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
TXE6 and RXE6 are synchronized by the base clock (f
enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of
the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set
within two clocks of the base clock, the transmission circuit or reception circuit may not
be initialized.
Set transmit data to TXB6 at least one base clock (f
Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
Fix the PS61 and PS60 bits to 0 when used in LIN communication operation.
Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
The operation of the PE6 bit differs depending on the set values of the PS61 and PS60
bits of asynchronous serial interface operation mode register 6 (ASIM6).
For the stop bit of the receive data, only the first bit is checked regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer register
6 (RXB6) but discarded.
If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6
when the peripheral hardware clock (f
CAUTIONS FOR WAIT.
To transmit data continuously, write the first transmit data (first byte) to the TXB6
register. Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data
(second byte) to the TXB6 register. If data is written to the TXB6 register while the
TXBF6 flag is “1”, the transmit data cannot be guaranteed.
To initialize the transmission unit upon completion of continuous transmission, be sure
to check that the TXSF6 flag is “0” after generation of the transmission completion
interrupt, and then execute initialization. If initialization is executed while the TXSF6
flag is “1”, the transmit data cannot be guaranteed.
Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting
the MDL67 to MDL60 bits.
ASICL6 can be refreshed (the same value is written) by software during a
communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7
and 5 (POWER6, RXE6) of ASIM6 = 1). However, do not set both SBRT6 and SBTT6
to 1 by a refresh operation during SBF reception (SBRT6 = 1) or SBF transmission
(until INTST6 occurs since SBTT6 has been set (1)), because it may re-trigger SBF
reception or SBF transmission.
In the case of an SBF reception error, the mode returns to the SBF reception mode.
The status of the SBRF6 flag is held (1).
Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of
ASIM6 = 1. After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is
completed (before an interrupt request signal is generated).
PRS
Cautions
) is stopped. For details, see CHAPTER 36
APPENDIX D LIST OF CAUTIONS
XCLK6
XCLK6
) after setting TXE6 = 1.
) set by CKSR6. To
X
D6 pin. If
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