UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 533

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(3) Automatic transmission/reception communication operation
(a) Automatic transmission/reception mode
Automatic transmission/reception can be performed using buffer RAM.
The data stored in the buffer RAM is output from the SOA0 pin via the SIOA0 register in synchronization with
the SCKA0 falling edge by performing (2) Automatic transmit/receive data setting.
The receive data is stored in the buffer RAM via the SIOA0 register in synchronization with the SCKA0 rising
edge.
Data transfer ends if bit 0 (TSF0) of serial status register 0 (CSIS0) is set to 1 when any of the following
conditions is met.
• Communication stop: Reset by clearing bit 7 (CSIAE0) of the CSIMA0 register to 0
• Communication suspension: Transfer of 1 byte is complete by setting bit 1 (ATSTP0) of the CSIT0 register
• Bit shift error: Transfer of 1 byte is complete when bit 1 (ERRF0) of the CSIS0 register becomes 1 while bit
• Transfer of the range specified by the ADTP0 register is complete
At this time, an interrupt request signal (INTACSI) is generated except when the CSIAE0 bit = 0.
If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read
automatic data transfer address count register 0 (ADTC0) to confirm how much of the data has already been
transferred and re-execute transfer by performing (2) Automatic transmit/receive data setting.
In addition, when busy control and strobe control are not performed, the BUSY0/BUZ/INTP7/P141 and
STB0/P145 pins can be used as ordinary I/O port pins.
Figure 17-13 shows the example of the operation timing in automatic transmission/reception mode and Figure
17-14 shows the operation flowchart. Figures 17-15 and 17-16 show the operation of internal buffer RAM
when 6 bytes of data are transmitted/received.
to 1
2 (ERRE0) = 1
CHAPTER 17 SERIAL INTERFACE CSIA0
533