UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 354

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
8.4 Operations of 8-Bit Timer/Event Counters 50 and 51
8.4.1 Operation as interval timer
count value preset to 8-bit timer compare register 5n (CR5n).
TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
(TCL5n).
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the
When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the
The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n
<1> Set the registers.
<2> After TCE5n = 1 is set, the count operation starts.
<3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> INTTM5n is generated repeatedly at the same interval.
Caution Do not write other values to CR5n during operation.
Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Remark Interval time = (N + 1) × t
Setting
TM5n count value
• TCL5n:
• CR5n:
• TMC5n:
Set TCE5n to 0 to stop the count operation.
Count clock
2. n = 0, 1
N = 01H to FFH
n = 0, 1
INTTM5n
TCE5n
CR5n
Select the count clock.
Compare value
Stop the count operation, select the mode in which clear & start occurs on a match of TM5n
and CR5n.
(TMC5n = 0000×××0B × = Don’t care)
Count start
00H
N
01H
Figure 8-11. Interval Timer Operation Timing (1/2)
t
(a) Basic operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
N
Clear
00H
Interrupt acknowledged
N
01H
Interval time
N
Clear
00H
Interrupt acknowledged
N
01H
Interval time
N
N
354