MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 141

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.4.1 Breakpoint Acknowledge Cycle
MC68HC16Y3/916Y3
USER’S MANUAL
Breakpoints stop program execution at a predefined point during system development.
In the MC68HC16Y3/916Y3, breakpoints are treated as a type of exception process-
ing. Breakpoints can be used alone or in conjunction with background debug mode.
The MC68HC16Y3/916Y3 has only one source and type of breakpoint. This is a
hardware breakpoint initiated by assertion of the BKPT input. Other modular
microcontrollers may have more than one source or type. The breakpoint
acknowledge cycle discussed here is the bus cycle that occurs as a part of breakpoint
exception processing when a breakpoint is initiated while background debug mode is
not enabled.
BKPT is sampled on the same clock phase as data. BKPT is valid, the data is tagged
as it enters the CPU16 pipeline. When BKPT is asserted while data is valid during an
instruction prefetch, the acknowledge cycle occurs immediately after that instruction
has executed. When BKPT is asserted while data is valid during an operand fetch, the
acknowledge cycle occurs immediately after execution of the instruction during which
it is latched. BKPT is asserted for only one bus cycle and a pipe flush occurs before
BKPT is detected by the CPU16, no acknowledge cycle occurs. To ensure detection,
BKPT should be asserted until a breakpoint acknowledge cycle is recognized.
When BKPT assertion is acknowledged by the CPU16, the MCU performs a word read
from CPU space address $00001E. This corresponds to the breakpoint number field
(ADDR[4:2]) and the type bit (T) being set to all ones (source 7, type 1). If this bus cycle
is terminated by BERR or by DSACK, the MCU performs breakpoint exception
processing. Refer to Figure 5-14 for a flow chart of the breakpoint operation. Refer to
the SCIM Reference Manual (SCIMRM/AD) for further information.
STOP BROADCAST
ACKNOWLEDGE
ACKNOWLEDGE
BREAKPOINT
LOW POWER
INTERRUPT
Figure 5-13 CPU Space Address Encoding
FUNCTION
1 1 1
2
1 1 1
2
1 1 1
2
CODE
0
0
0
23
23
23
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ADDRESS BUS
CPU SPACE
TYPE FIELD
19
19
19
CPU SPACE CYCLES
16
16
16
4
BKPT#
LEVEL
2
1
T 0
0
0
0
1
MOTOROLA
CPU SPACE CYC TIM
5-33