MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 98

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.11 Execution Process
4.11.1 Changes in Program Flow
4.12 Instruction Timing
4-36
MOTOROLA
Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are
evaluated in stage B. The execution unit can access operands in either stage A or
stage B (stage B accesses are limited to 8-bit operands). When execution is complete,
opcodes are moved from stage B to stage C, where they remain until the next
instruction is complete.
A prefetch mechanism in the microsequencer reads instruction words from memory
and increments the program counter. When instruction execution begins, the program
counter points to an address six bytes after the address of the first word of the
instruction being executed.
The number of machine cycles necessary to complete an execution sequence varies
according to the complexity of the instruction. Refer to the CPU16 Reference Manual
(CPU16RM/AD) for details.
When program flow changes, instructions are fetched from a new address. Before ex-
ecution can begin at the new address, instructions and operands from the previous in-
struction stream must be removed from the pipeline. If a change in flow is temporary,
a return address must be stored, so that execution of the original instruction stream
can resume after the change in flow.
When an instruction that causes a change in program flow executes, PK : PC point to
the address of the first word of the instruction + $0006. During execution of the
instruction, PK : PC is loaded with the address of the first instruction word in the new
instruction stream. However, stages A and B still contain words from the old instruction
stream. Extra processing steps must be performed before execution from the new
instruction stream.
The execution time of CPU16 instructions has three components:
A bus cycle requires a minimum of two system clock periods. If the access time of a
memory device is greater than two clock periods, bus cycles are longer. However, all
bus cycles must be an integer number of clock periods. CPU16 internal operations are
always an integer multiple of two clock periods.
Dynamic bus sizing affects bus cycle time. The integration module manages all ac-
cesses. Refer to SECTION 5 SINGLE-CHIP INTEGRATION MODULE 2 for more in-
formation.
The CPU16 does not execute more than one instruction at a time. The total time
required to execute a particular instruction stream can be calculated by summing the
individual execution times of each instruction in the stream.
• Bus cycles required to prefetch the next instruction
• Bus cycles required for operand accesses
• Time required for internal operations
MC68HC16Y3/916Y3
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