MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 203

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.4.2 Bootstrap Operation
9.4.3 Normal Operation
9.4.4 TPU Mode Operation
MC68HC16Y3/916Y3
USER’S MANUAL
If the state of the STOP shadow bit is one, or data bus pin DATA12 is pulled low during
reset, the STOP bit in TFMCR is set during reset and the TPUFLASH array is disabled.
The module does not respond to array or bootstrap vector accesses until the STOP bit
is cleared. This allows an external device to respond to accesses to the TPUFLASH
array address space or to bootstrap accesses. The erased state of the shadow bits is
one. An erased module comes out of reset in STOP mode.
After reset, the CPU16 begins bootstrap operation by fetching initial values for its in-
ternal registers from IMB addresses $000000 through $000006 in program space.
These are the addresses of the bootstrap vectors in the exception vector table. If
BOOT = 0 and STOP = 0 in TFMCR during reset, the TPUFLASH module is configured
to respond to bootstrap vector accesses. Table 9-1 shows the vector assignments.
As soon as address $000006 has been read, TPUFLASH operation returns to normal,
and the module no longer responds to bootstrap vector accesses.
If the TPU flash is configured for bootstrap operation, as well as to enter TPU mode
automatically out of reset (TME = 0), the TPUFLASH first performs the bootstrap ac-
cesses, then provides microcode to the TPU2.
The TPUFLASH allows a byte or aligned-word read in one bus cycle. Long-word reads
require two bus cycles.
The module checks function codes to verify address space access type. Array access-
es are defined by the state of ASPC[1:0] in TFMCR. When the TPUFLASH is config-
ured for normal operation, the array responds to read accesses only; write operations
are ignored.
When in TPU mode, array data cannot be written from the IMB. It is also impossible to
program/erase the TPUFLASH while in TPU Mode. Control registers can be read, but
not written to. TPU mode is entered either by setting the emulation control (EMU) bit
in the TPU2 module configuration register (TPUMCR), or by setting the TPU mode en-
able shadow (TME) bit in the TPUFLASH module configuration register (TFMCR).
EEPROM Bootstrap Word
TFBS0
TFBS1
TFBS2
TFBS3
Table 9-1 Bootstrap Vector Assignments
TPU FLASH EEPROM MODULE
IMB Vector Address
$000000
$000002
$000004
$000006
MCU Reset Vector Content
Initial ZK, SK, and PK
Initial PC
Initial SP
Initial IZ
MOTOROLA
9-3