MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 190

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.3 MRM Array Address Space Type
7.4 Normal Access
7-2
MOTOROLA
LOCK can be written once only to a value of one. This prevents accidental remapping
of the array.
ASPC[1:0] in MRMCR determines ROM array address space type. The module can
respond to both program and data space accesses or to program space accesses
only. This allows code to be executed from ROM, and permits use of program counter
relative addressing mode for operand fetches from the array.
In addition, ASPC[1:0] specify whether access to the MRM can be made in supervisor
mode only, or in either user or supervisor mode. Because the CPU16 operates in su-
pervisor mode only, ASPC1 has no effect.
The default value of ASPC[1:0] is established during mask programming, but field val-
ue can be changed after reset if the LOCK bit in the MRMCR has not been masked to
a value of one.
Table 7-1 shows ASPC[1:0] field encodings.
Refer to 4.6 Addressing Modes for more information on addressing modes. Refer to
5.5.1.7 Function Codes for more information concerning address space types and pro-
gram/data space access.
The array can be accessed by byte, word, or long word. A byte or aligned word access
takes one bus cycle or two system clocks. A long word or misaligned word access re-
quires two bus cycles. Refer to 5.6 Bus Operation for more information concerning ac-
cess times.
Access time can be optimized for a particular application by inserting wait states into
each access. The number of wait states inserted is determined by the value of
WAIT[1:0] in the MRMCR. Two, three, four, or five bus-cycle accesses can be speci-
fied. The default value WAIT[1:0] is established during mask programming, but field
value can be changed after reset if the LOCK bit in the MRMCR has not been masked
to a value of one.
Table 7-2 shows WAIT[1:0] field encodings.
Table 7-1 ROM Array Space Field
ASPC[1:0]
X0
X1
MASKED ROM MODULE
Program and data accesses
Program access only
State Specified
MC68HC16Y3/916Y3
USER’S MANUAL