MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 322

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.6 Host Interface Registers
14.6.1 System Configuration Registers
14.6.1.1 Prescaler Control for TCR1
14-14
MOTOROLA
The TPU2 memory map contains three groups of registers:
All registers except the channel interrupt status register (CISR) must be read or written
by means of word accesses. The address space of the TPU2 memory map occupies
512 bytes. Unused registers within the 512-byte address space return zeros when
read.
The TPU2 configuration control registers, TPUMCR, TPUMCR2, and TICR, define
TPU2 module attributes. Refer to D.10.1 TPU2 Module Configuration Register,
D.10.15 TPUMCR2 Module Configuration Register 2 and D.10.5 TPU2 Interrupt Con-
figuration Register for more information about TPUMCR, TPUMCR2, and TICR.
Timer count register 1 (TCR1) is clocked from the output of a prescaler. Two fields
(PSCK, TCR1P) in TPUMCR and one field (DIV2) in TPUMCR2 control TCR1. The
prescaler's input is the internal TPU system clock divided by either 2, 4, or 32, depend-
ing on the value of the PSCK bit and the DIV2 bit. If the DIV2 bit is one, the TCR1
counter increments at a rate of the internal clock divided by two. If DIV2 is zero, the
TCR1 increment rate is defined by the values in Table 14-1.The prescaler divides this
input by 1, 2, 4, or 8, depending on the value of TCR1P. Channels using TCR1 have
the capability to resolve down to the TPU system clock divided by 4.
Figure 14-2 shows a diagram of the TCR1 prescaler control block.
• System configuration registers
• Channel control and status registers
• Development support and test verification registers
Table 14-1 TCR1 Prescaler Control Bits
TCR1P[1:0]
00
01
10
11
TIME PROCESSOR UNIT 2
Divide By
Prescaler
1
2
4
8
PSCK = 0
f
f
f
f
sys
sys
sys
sys
TCR1 Clock Input
128
256
32
64
PSCK = 1
f
f
f
f
sys
sys
sys
sys
16
32
4
8
MC68HC16Y3/916Y3
USER’S MANUAL