MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 220

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.7.6 Conversion Timing
10-12
MOTOROLA
Total conversion time is made up of initial sample time, transfer time, final sample time,
and resolution time. Initial sample time is the time during which a selected input chan-
nel is connected to the sample buffer amplifier through a sample capacitor. During
transfer time, the sample capacitor is disconnected from the multiplexer, and the RC
DAC array is driven by the sample buffer amp. During final sampling time, the sample
capacitor and amplifier are bypassed, and the multiplexer input charges the RC DAC
array directly. During resolution time, the voltage in the RC DAC array is converted to
a digital value, and the value is stored in the SAR.
Initial sample time and transfer time are fixed at two ADC clock cycles each. Final sam-
ple time can be 2, 4, 8, or 16 ADC clock cycles, depending on the value of the STS
field in ADCTL0. Resolution time is ten cycles for 8-bit conversion and twelve cycles
for 10-bit conversion.
Transfer and resolution require a minimum of 16 ADC clocks (8 s with a 2.1 MHz ADC
clock) for 8-bit resolution or 18 ADC clocks (9 s with a 2.1 MHz ADC clock) for 10-bit
resolution. If maximum final sample time (16 ADC clocks) is used, total conversion
time is 15 s for an 8-bit conversion or 16 s for a 10-bit conversion (with a 2.1 MHz
ADC clock).
Figures 10-2 and 10-3 illustrate the timing for 8- and 10-bit conversions, respectively.
These diagrams assume a final sampling period of two ADC clocks.
SAMPLE
INITIAL
TIME
CH 1
SCF FLAG SET HERE AND SEQUENCE
1
SAMPLE AND TRANSFER
ENDS IF IN THE 4-CHANNEL MODE
TRANSFER
6 CYCLES
PERIOD
TIME
CH 2
Figure 10-2 8-Bit Conversion Timing
(2 ADC CLOCKS)
ANALOG-TO-DIGITAL CONVERTER
SAMPLE
FINAL
TIME
CH 3
CYCLES
CH 4
SAR7
2
CYCLE
SUCCESSIVE APPROXIMATION
SAR6
1
CH 5
SCF FLAG SET HERE AND SEQUENCE
RESOLUTION TIME
CYCLE
SAR5
ENDS IF IN THE 8-CHANNEL MODE
1
SEQUENCE
CYCLE
SAR4
1
CH 6
CYCLE
SAR3
1
CYCLE
SAR2
1
CH 7
CYCLE
SAR1
TRANSFER CONVERSION TO
RESULT REGISTER AND SET
1
CYCLE
SAR0
1
MC68HC16Y3/916Y3
CH 8
CYCLE
END
USER’S MANUAL
CCF
EOC
1
16
16 ADC 8-BIT TIM 1