MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 185

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.1 SRAM Register Block
6.2 SRAM Array Address Mapping
MC68HC16Y3/916Y3
USER’S MANUAL
The standby RAM (SRAM) module consists of a fixed-location control register block
and an array of fast (two clock) static RAM that may be mapped to a user specified
location in the system memory map. The MC68HC16Y3 uses a 4-Kbyte array; the
MC68HC916Y3 uses a 2-Kbyte array. The SRAM is especially useful for system
stacks and variable storage. The SRAM can be mapped to any address that is a mul-
tiple of the array size so long as SRAM boundaries do not overlap the module control
registers (overlap makes the registers inaccessible). Data can be read/written in bytes,
words or long words. SRAM is powered by V
down, SRAM contents can be maintained by power from the V
switching between sources is automatic.
There are four SRAM control registers: the RAM module configuration register
(RAMMCR), the RAM test register (RAMTST), and the RAM array base address reg-
isters (RAMBAH/RAMBAL).
The module mapping bit (MM) in the SCIM configuration register (SCIMCR) defines
the most significant bit (ADDR23) of the IMB address for each MC68HC16Y3/916Y3
module. Because ADDR[23:20] are driven to the same value as ADDR19, MM must
be set to one. If MM is cleared, IMB modules are inaccessible. For more information
about how the state of MM affects the system, refer to 5.2.1 Module Mapping.
The SRAM control register consists of eight bytes, but not all locations are implement-
ed. Unimplemented register addresses are read as zeros, and writes have no effect.
Refer to D.3 Standby RAM Module for register block address map and register bit/field
definitions.
Base address registers RAMBAH and RAMBAL are used to specify the SRAM array
base address in the memory map. RAMBAH and RAMBAL can only be written while
the SRAM is in low-power stop mode (RAMMCR STOP = 1) and the base address lock
(RAMMCR RLCK = 0) is disabled. RLCK can be written once only to a value of one;
subsequent writes are ignored. This prevents accidental remapping of the array.
In the CPU16, ADDR[23:20] follow the logic state of ADDR19. The
SRAM array must not be mapped to addresses $080000–$7FFFFF,
which are inaccessible to the CPU16. If mapped to these addresses,
the array remains inaccessible until a reset occurs, or it is remapped
outside of this range.
SECTION 6STANDBY RAM MODULE
STANDBY RAM MODULE
NOTE
DD
in normal operation. During power-
STBY
input. Power
MOTOROLA
6-1