MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 157

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.7.3.7 Breakpoint Mode Selection
5.7.3.8 Emulation Mode Selection
MC68HC16Y3/916Y3
USER’S MANUAL
Background debug mode (BDM) is enabled when the breakpoint (BKPT) pin is
sampled at a logic level zero at the release of RESET. Subsequent assertion of the
BKPT pin or the internal breakpoint signal (for instance, the execution of the CPU16
BKPT instruction) will place the CPU16 in BDM.
If BKPT is sampled at a logic level one at the rising edge of RESET, BDM is disabled.
Assertion of the BKPT pin or execution of the BKPT instruction will result in normal
breakpoint exception processing.
BDM remains enabled until the next system reset. BKPT is relatched on each rising
transition of RESET. BKPT is internally synchronized and must be held low for at least
two clock cycles prior to RESET negation for BDM to be enabled. BKPT assertion logic
must be designed with special care. If BKPT assertion extends into the first bus cycle
following the release of RESET, the bus cycle could inadvertently be tagged with a
breakpoint.
Refer to 4.14.4 Background Debug Mode and the CPU16 Reference Manual
(CPU16RM/AD) for more information on background debug mode. Refer to the SCIM
Reference Manual (SCIMRM/AD) and APPENDIX A ELECTRICAL CHARACTERIS-
TICS for more information concerning BKPT signal timing.
The SCIM2 contains logic that can be used to replace on-chip ports externally. The
SCIM2 also contains special support logic that allows external emulation of internal
ROM. This emulation support feature enables the development of a single-chip appli-
cation in expanded mode.
Emulator mode is a special type of 16-bit expanded operation. It is entered by holding
DATA10 low, BERR high, and DATA1 low during reset. In emulator mode, all port A,
B, E, G, and H data and data direction registers and the port E pin assignment register
are mapped externally. Port C data, port F data and data direction registers, and port
F pin assignment register are accessible normally in emulator mode.
An emulator chip select (CSE) is asserted whenever any of the externally-mapped
registers are addressed. The signal is asserted on the falling edge of AS. The SCIM2
does not respond to these accesses, allowing external logic, such as a port replace-
ment unit (PRU) to respond. Accesses to externally mapped registers require three
clock cycles.
The MODCLK pin can also be used as parallel I/O pin PF0. To pre-
vent inadvertent clock mode selection by logic connected to port F,
use an active device to drive MODCLK during reset.
The masked ROM is available only on the MC68HC16Y3.
NOTE
NOTE
MOTOROLA
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