MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 163

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.7.10 Reset Status Register
5.8 Interrupts
MC68HC16Y3/916Y3
USER’S MANUAL
The following events take place when MSTRST is negated after assertion.
Vectors can be fetched from internal RAM or from external ROM enabled by the
CSBOOT signal.
The reset status register (RSR) contains a bit for each reset source in the MCU. When
a reset occurs, a bit corresponding to the reset type is set. When multiple causes of
reset occur at the same time, more than one bit in RSR may be set. The reset status
register is updated by the reset control logic when the RESET signal is released. Refer
to APPENDIX D REGISTER SUMMARY.
Interrupt recognition and servicing involve complex interaction between the SCIM2,
the CPU16, and a device or module requesting interrupt service. This discussion pro-
vides an overview of the entire interrupt process. Chip-select logic can also be used
to respond to interrupt requests. Refer to 5.9 Chip-Selects for more information.
1. Instruction execution is aborted.
2. The condition code register is initialized.
3. The K register is cleared.
1. The CPU16 samples the BKPT input.
2. The CPU16 fetches RESET vectors in the following order:
3. The CPU16 begins fetching instructions pointed to by the initial PK: PC.
a. The IP field is set to $7, disabling all interrupts below priority 7.
b. The S bit is set, disabling LPSTOP mode.
c. The SM bit is cleared, disabling MAC saturation mode.
a. Initial ZK, SK, and PK extension field values
b. Initial PC
c. Initial SP
d. Initial IZ value
All CCR bits that are not initialized are not affected by reset.
However, out of power-on reset, these bits are indeterminate.
NOTE
MOTOROLA
5-55