AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 337

• Manufacturer Part Number: AT91SAM7S256C-MU
• Description: IC ARM7 MCU 32BIT 256K 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S256-MU; AT91SAM7S256-MU

30.9.5.4
Figure 30-27. Clock Synchronization in Read Mode
Notes:
6175K–ATARM–30-Aug-10
TWI_THR
TXCOMP
SVREAD
Clock Synchronization in Read Mode
SCLWS
SVACC
TXRDY
TWCK
1. TXRDY is reset when data has been written in the TWI_TH to the shift register and set when this data has been acknowl-
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
3. SCLWS is automatically set when the clock synchronization mechanism is started.
edged or non acknowledged.
SADR.
Clock Synchronization
1
2
S
S
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
As soon as a START is detected
SADR
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emp-
tied before the emission/reception of a new character. In this case, to avoid sending/receiving
undesired data, a clock stretching mechanism is implemented.
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition
was not detected. It is tied low until the shift register is loaded.
Figure 30-27 on page 337
DATA0
DATA0
R
Write THR
A
1
DATA0
A
describes the clock synchronization in Read mode.
DATA1
DATA1
CLOCK is tied low by the TWI
AT91SAM7S Series Preliminary
as long as THR is empty
A
XXXXXXX
2
DATA2
DATA2
Ack or Nack from the master
NA
S
337