AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 486

• Manufacturer Part Number: AT91SAM7S256C-MU
• Description: IC ARM7 MCU 32BIT 256K 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S256-MU; AT91SAM7S256-MU

34.5.3.4
34.6
Table 34-2.
Note:
486
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x4C - 0xFC
0x100 - 0x1FC
0x200 + ch_num * 0x20 + 0x00
0x200 + ch_num * 0x20 + 0x04
0x200 + ch_num * 0x20 + 0x08
0x200 + ch_num * 0x20 + 0x0C
0x200 + ch_num * 0x20 + 0x10
(1)
Pulse Width Modulation Controller (PWM) User Interface
1. Some registers are indexed with “ch_num” index ranging from 0 to X-1.
AT91SAM7S Series Preliminary
Interrupts
Register Mapping
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end
of the corresponding channel period. The interrupt remains active until a read operation in the
PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A chan-
nel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.
Register
PWM Mode Register
PWM Enable Register
PWM Disable Register
PWM Status Register
PWM Interrupt Enable Register
PWM Interrupt Disable Register
PWM Interrupt Mask Register
PWM Interrupt Status Register
Reserved
Reserved
PWM Channel Mode Register
PWM Channel Duty Cycle Register
PWM Channel Period Register
PWM Channel Counter Register
PWM Channel Update Register
Name
PWM_MR
PWM_ENA
PWM_DIS
PWM_SR
PWM_IER
PWM_IDR
PWM_IMR
PWM_ISR
PWM_CMR
PWM_CDTY
PWM_CPRD
PWM_CCNT
PWM_CUPD
–
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-only
Write-only
Access
–
6175K–ATARM–30-Aug-10
Reset
0x0
0x0
0x0
0x0
0
0
0
0
–
-
-
-
-
-