AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 54

IC ARM7 MCU 32BIT 256K 64-QFN

AT91SAM7S256C-MU

Manufacturer Part Number
AT91SAM7S256C-MU
Description
IC ARM7 MCU 32BIT 256K 64-QFN
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM7S256C-MU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT91
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
SPI, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
AT91SAM7S256-MU
AT91SAM7S256-MU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S256C-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
54
AT91SAM7S Series Preliminary
Table 12-3.
Bit Number
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AT91SAM7Sxx JTAG Boundary Scan Register (Continued)
PA7/PGMNVALID
PA4/PGMNCMD
PA25/PGMD13
PA26/PGMD14
PA27/PGMD15
PA6/PGMNOE
PA11/PGMM3
PA10/PGMM2
PA5/PGMRDY
PA9/PGMM1
PA8/PGMM0
Pin Name
Pin Type
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
6175K–ATARM–30-Aug-10
Associated BSR
CONTROL
CONTROL
CONTROL
OUTPUT
OUTPUT
OUTPUT
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Cells
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

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