AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 758

• Manufacturer Part Number: AT91SAM7S256C-MU
• Description: IC ARM7 MCU 32BIT 256K 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S256-MU; AT91SAM7S256-MU

748
Version
6175I
Comments
Overview:
Section
Communication”
Section 7.4 ”Peripheral DMA
Section 9. ”System
Section 9.1.1 ”Brownout Detector and Power-on
Section 12.5.5 ”ID Code
Section 9.5 ”Debug
Rev B to the list.
ADC:
Figure 36-1 ”Analog-to-Digital Converter Block Diagram”
Section 36.6.2 ”ADC Mode
Section 36.5.5 ”Conversion
PMC:
“PMC Interrupt Enable
Register”, LOCKU and UOSCS removed from bit fields in register tables.
Section 25.7 ”Programming
devices having 12 peripheral clocks
Section 25.9.10 ”PMC Master Clock
Section 25.9 ”Power Management Controller (PMC) User
RSTC;
Section 13.3.4.4 ”Software
Electrical Characteristics:
Table 37-2, “DC
Table 37-4, “Brownout Detector
Table 37-19, “External Voltage Reference
Section 37.10.2 ”SSC
Ordering Information:
Table 39-1, “LQFP/QFN Ordering
versions.
Section 40. ”Errata”
Section 40.2 ”Errata Summary by Product and Revision or Manufacturing
Section 40-1 ”Errata Summary
Chip ID noted on products where no chip ID errata exists.
Section 40.16 ”AT91SAM7S64 Errata - Revision B
Section 40.21 ”AT91SAM7S32 Errata - Revision B
USART: XOFF Character Bad Behavior, removed from all revisions of the AT91SAM7S series components.
AT91SAM7S Series Preliminary
”Features”,
Characteristics”, CMOS conditions added to I
Controller”,
Unit”, the list;
“Debug Unit (DBGU)”
Characteristics”, added to datasheet.
Register”,
Register”, added “The JTAG ID is used in the IEEE 1149.1 JTAG Boundary Scan.”
Reset”; updated list with details on PERRST and PROCRST.
Register”, updated the formula on bit description:
Triggers”, update to the third paragraph detailing hardware trigger.
Sequence”, Step
Controller”, added list of PDC priorities.
Table”, added to Errata.
Figure 9-1
Characteristics”, V
“PMC Interrupt Disable
“Chip ID
Information”, Updated product ordering information by MRL A and MRL B
Register”, MDIV removed from bit fields in register table.
and
Input”, added ADVREF Input w/conditions “8-bit resolution mode”.
updated with
Registers”, chip IDs updated, added SAM7S32 Rev B and SAM7S64
6 “Enabling Peripheral
Figure 9-2
Reset”, fourth paragraph reduced.
BOT
Parts”, added to Errata.
Parts”, removed errata for NVM and Voltage Regulator.
conditions = Falling edge.
“Mode for General Purpose 2-wire UART Serial
Register”,
VDDANA replaced by VDDIN. PMC added to figure
RTT is reset by “power_on_reset”.
Interface”, added PMC_PCK2 to Register Mapping.
O
for V
“PMC Status
OL
Clocks”, AT91SAM7S512 grouped with
and V
Number”, added to Errata.
OH
“SHTIM: Sample & Hold Time”
.
Register”,
“PMC Interrupt Mask
6175K–ATARM–30-Aug-10
.
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