AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 704

• Manufacturer Part Number: AT91SAM7S256C-MU
• Description: IC ARM7 MCU 32BIT 256K 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S256-MU; AT91SAM7S256-MU

40.16.7
40.16.7.1
40.16.7.2
40.16.7.3
704
AT91SAM7S Series Preliminary
Synchronous Serial Controller (SSC)
SSC: Periodic Transmission Limitations in Master Mode
SSC: Transmitter Limitations in Slave Mode
SSC: Transmitter Limitations in Slave Mode
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not
sent.
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when the start of edge (rising or falling) of synchro has a Start Delay equal to zero.
None.
If TK is programmed as an input and TF is programmed as an output and requested to be set to
low/high during data emission, the Frame Synchro signal is generated one bit clock period after
the data start and one data bit is lost. This problem does not exist when generating a periodic
synchro.
The data need to be delayed for one bit clock period with an external assembly.
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6175K–ATARM–30-Aug-10