AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 701

• Manufacturer Part Number: AT91SAM7S256C-MU
• Description: IC ARM7 MCU 32BIT 256K 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S256-MU; AT91SAM7S256-MU

40.16.4
40.16.4.1
40.16.4.2
40.16.4.3
40.16.4.4
40.16.4.5
40.16.5
40.16.5.1
6175K–ATARM–30-Aug-10
Pulse Width Modulation Controller (PWM)
Real Time Timer (RTT)
PWM: Update when PWM_CCNTx = 0 or 1
PWM: Update when PWM_CPRDx = 0
PWM: Counter Start Value
PWM: Constraints on Duty Cycle Value
PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
RTT: Possible Event Loss when Reading RTT_SR
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Check the Channel Counter Register before writing the update register.
When Channel Period Register equals 0, the period update is not operational.
Do not write 0 in the period register.
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
None.
Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in
left aligned mode may change the polarity of the signal.
Do not set PWM_CDTYx at 0 in center aligned mode.
Do not set PWM_CDTYx at 0 or 1 in left aligned mode.
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled
by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of
the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit
in the PWM_SR stays at 1.
Do not disable a channel before completion of one period of the selected clock.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the
RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event.
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
AT91SAM7S Series Preliminary
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