S9S08DZ60F1MLH Freescale Semiconductor, S9S08DZ60F1MLH Datasheet - Page 11

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S9S08DZ60F1MLH

Manufacturer Part Number
S9S08DZ60F1MLH
Description
MCU 60K FLASH MASK AUTO 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of S9S08DZ60F1MLH

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LQFP
Processor Series
S08D
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
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Section Number
6.4
6.5
7.1
7.2
7.3
7.4
7.5
8.1
Freescale Semiconductor
Pin Behavior in Stop Modes.............................................................................................................88
Parallel I/O and Pin Control Registers .............................................................................................89
Introduction ....................................................................................................................................115
Programmer’s Model and CPU Registers ......................................................................................116
Addressing Modes..........................................................................................................................119
Special Operations..........................................................................................................................121
HCS08 Instruction Set Summary ...................................................................................................124
Introduction ....................................................................................................................................135
6.3.2 Edge and Level Sensitivity ................................................................................................88
6.3.3 Pull-up/Pull-down Resistors .............................................................................................88
6.3.4 Pin Interrupt Initialization .................................................................................................88
6.5.1 Port A Registers ................................................................................................................90
6.5.2 Port B Registers ................................................................................................................94
6.5.3 Port C Registers ................................................................................................................98
6.5.4 Port D Registers ..............................................................................................................101
6.5.5 Port E Registers ...............................................................................................................105
6.5.6 Port F Registers ...............................................................................................................108
6.5.7 Port G Registers ..............................................................................................................111
7.1.1 Features ...........................................................................................................................115
7.2.1 Accumulator (A) .............................................................................................................116
7.2.2 Index Register (H:X) .......................................................................................................116
7.2.3 Stack Pointer (SP) ...........................................................................................................117
7.2.4 Program Counter (PC) ....................................................................................................117
7.2.5 Condition Code Register (CCR) .....................................................................................117
7.3.1 Inherent Addressing Mode (INH) ...................................................................................119
7.3.2 Relative Addressing Mode (REL) ...................................................................................119
7.3.3 Immediate Addressing Mode (IMM) ..............................................................................119
7.3.4 Direct Addressing Mode (DIR) ......................................................................................119
7.3.5 Extended Addressing Mode (EXT) ................................................................................120
7.3.6 Indexed Addressing Mode ..............................................................................................120
7.4.1 Reset Sequence ...............................................................................................................121
7.4.2 Interrupt Sequence ..........................................................................................................121
7.4.3 Wait Mode Operation ......................................................................................................122
7.4.4 Stop Mode Operation ......................................................................................................122
7.4.5 BGND Instruction ...........................................................................................................123
8.1.1 Features ...........................................................................................................................137
Multi-Purpose Clock Generator (S08MCGV1)
Central Processor Unit (S08CPUV3)
MC9S08DZ60 Series Data Sheet, Rev. 4
Chapter 7
Chapter 8
Title
Page
11

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