S9S08DZ60F1MLH Freescale Semiconductor, S9S08DZ60F1MLH Datasheet - Page 73

• Manufacturer Part Number: S9S08DZ60F1MLH
• Description: MCU 60K FLASH MASK AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ60F1MLH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Resets, Interrupts, and General System Control
The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pull-up
or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down,
the IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
5.5.2.2
Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In the
edge and level detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ
pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be
cleared) as long as the IRQ pin remains at the asserted level.
5.5.3
Interrupt Vectors, Sources, and Local Masks
Table 5-1
provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU
registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
73