S9S08DZ60F1MLH Freescale Semiconductor, S9S08DZ60F1MLH Datasheet - Page 383

• Manufacturer Part Number: S9S08DZ60F1MLH
• Description: MCU 60K FLASH MASK AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ60F1MLH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
3
4
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
Freescale Semiconductor
Typical data was characterized at 5.0 V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of t
clock frequency changes to the untrimmed DCO frequency (freset = (f
reset to 0; and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
Timing is shown with respect to 20% V
Nu
m
1
2
3
4
5
6
7
8
D/
D
D
D
D
D
P
T
T
C
Control Timing
Bus frequency (t
Internal low-power oscillator period
External reset pulse width
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ/PIAx/ PIBx/PIDx pulse width
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Asynchronous path
Synchronous path
RESET PIN
Slew rate control disabled (PTxSE = 0)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
3
cyc
= 1/f
3
2
Rating
Bus
2
DD
)
MC9S08DZ60 Series Data Sheet, Rev. 4
and 80% V
Table A-13. Control Timing
Figure A-2. Reset Timing
DD
levels. Temperature range –40°C to 125°C.
4
4
t
extrst
t
t
t
dco_ut
Rise
Rise
Symbol
ILIH,
t
t
t
MSSU
t
t
rstdrv
f
extrst
MSH
LPO
Bus
, t
, t
t
IHIL
)/4) because TRIM is reset to 0x80 and FTRIM is
Fall
Fall
1.5 x t
34 x t
1.5 t
100
Min
dc
—
25
25
—
—
—
—
cyc
cyc
cyc
Appendix A Electrical Characteristics
cyc
Typical
. After POR reset, the bus
1500
40
75
11
35
—
—
1
Max
20
—
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
ns
ns
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