S9S08DZ60F1MLH Freescale Semiconductor, S9S08DZ60F1MLH Datasheet - Page 147

• Manufacturer Part Number: S9S08DZ60F1MLH
• Description: MCU 60K FLASH MASK AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ60F1MLH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
8.4.1.1
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
In FLL engaged internal mode, the MCGOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL clock frequency locks to 1024 times the reference frequency, as
selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power
state.
8.4.1.2
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FLL engaged external mode, the MCGOUT clock is derived from the FLL clock which is controlled by
the external reference clock. The external reference clock which is enabled can be an external
crystal/resonator or it can be another external clock source.The FLL clock frequency locks to 1024 times
the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the
PLL is disabled in a low power state.
8.4.1.3
In FLL bypassed internal (FBI) mode, the MCGOUT clock is derived from the internal reference clock
and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire
its target frequency while the MCGOUT clock is driven from the internal reference clock.
The FLL bypassed internal mode is entered when all the following conditions occur:
Freescale Semiconductor
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CLKS bits are written to 00
IREFS bit is written to 1
PLLS bit is written to 0
RDIV bits are written to 000. Since the internal reference clock frequency should already be in the
range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.
CLKS bits are written to 00
IREFS bit is written to 0
PLLS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
CLKS bits are written to 01
IREFS bit is written to 1
PLLS bit is written to 0
RDIV bits are written to 000. Since the internal reference clock frequency should already be in the
range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.
FLL Engaged Internal (FEI)
FLL Engaged External (FEE)
FLL Bypassed Internal (FBI)
MC9S08DZ60 Series Data Sheet, Rev. 4
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
147