EM357-RTR Ember, EM357-RTR Datasheet - Page 152

• Manufacturer Part Number: EM357-RTR
• Description: IC RF TXRX ZIGBEE 192KB 48QFN
• Manufacturer: Ember

Specifications of EM357-RTR

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 26mA
• Current - Transmitting: 31mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1011-2

9.3.14.4
This example sets the enable of Timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of
Timer 1. To ensure the counters are aligned, Timer 1 must be configured in master/slave mode (slave with
respect to TI1, master with respect to Timer 2):
When a rising edge occurs on TI1 (Timer 1), both counters start counting synchronously on the internal clock
and both timers’ INT_TIMTIF flags are set. Figure 9-36 shows this in operation.
Note: In this example both timers are initialized before starting by setting their respective TIM_UG bits. Both
counters starts from 0, but an offset can be inserted between them by writing any of the counter registers
(TIMx_CNT). The master/slave mode inserts a delay between CNT_EN and CK_PSC on Timer 1.
Configure Timer 1 in master mode to send its Enable as trigger output: Write TIM_MMS = 001 in the
TIM1_CR2 register.
Configure Timer 1 slave mode to get the input trigger from TI1: Write TIM_TS = 100 in the TIM1_SMCR
register.
Configure Timer 1 in trigger mode: Write TIM_SMS = 110 in the TIM1_SMCR register.
Configure the Timer 1 in master/slave mode: Write TIM_MSM = 1 in the TIM1_SMCR register.
Configure Timer 2 to get the input trigger from Timer 1: Write TIM_TS = 000 in the TIM2_SMCR register.
Configure Timer 2 in trigger mode: Write TIM_SMS = 110 in the TIM2_SMCR register.
Starting both Timers Synchronously in Response to an External Trigger
Figure 9-35. Triggering Timer 2 with Enable of Timer 1
Final
9-28
120-035X-000G