EM357-RTR Ember, EM357-RTR Datasheet - Page 42
EM357-RTR
Manufacturer Part Number
EM357-RTR
Description
IC RF TXRX ZIGBEE 192KB 48QFN
Manufacturer
Ember
Specifications of EM357-RTR
Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
5dBm
Sensitivity
-100dBm
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
26mA
Current - Transmitting
31mA
Data Interface
PCB, Surface Mount
Memory Size
192kB Flash, 12kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1011-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EM357-RTR
Manufacturer:
SILICON
Quantity:
3 000
Part Number:
EM357-RTR
Manufacturer:
SILICON
Quantity:
20 000
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6.2.1.2 nRESET Pin
A single active low pin, nRESET, is provided to reset the system. This pin has a Schmitt triggered input.
To afford good noise immunity and resistance to switch bounce, the pin is filtered with the Reset Filter
module and generates the pin reset source, nRESET, to the Reset Generation module. Table 6-4 contains the
specification for the filter.
6.2.1.3 Watchdog Reset
The EM35x contains a watchdog timer (see also the Watchdog Timer section) that is clocked by the internal
1 kHz timing reference. When the timer expires it generates the reset source WATCHDOG_RESET to the Reset
Generation module.
6.2.1.4 Software Reset
The ARM
SYSRESETREQ to the Reset Generation module.
6.2.1.5 Option Byte Error
The flash memory controller contains a state machine that reads configuration information from the
information blocks in the flash at system start time. An error check is performed on the option bytes that are
read from flash and, if the check fails, an error is signaled that provides the reset source OPT_BYTE_ERROR to
the Reset Generation module.
If an option byte error is detected, the system restarts and the read and check process is repeated. If the
error is detected again the process is repeated but stops on the 3
emulated deep sleep where recovery is possible. In this state, flash memory readout protection is forced
active to prevent secure applications from being compromised.
6.2.1.6 Debug Reset
The Serial Wire/JTAG Interface (SWJ) provides access to the SWJ Debug Port (SWJ-DP) registers. By setting
the register bit CDBGRSTREQ in the SWJ-DP, the reset source CDBGRSTREQ is provided to the Reset
Generation module.
6.2.1.7 JRST
One of the EM35x’s pins can function as the JTAG reset, conforming to the requirements of the JTAG
standard. This input acts independently of all other reset sources and, when asserted, does not reset any on-
chip hardware except for the JTAG TAP. If the EM35x is in the Serial Wire mode or if the SWJ is disabled, this
input has no effect.
Parameter
Reset filter time constant
Reset pulse width to guarantee a reset
Reset pulse width guaranteed not to cause a reset
®
Cortex
TM
-M3 CPU can initiate a reset under software control. This is indicated with the reset source
Table 6-4. Reset Filter Specification for nRESET
Final
6-4
rd
failure. The system is then placed into an
EM351 / EM357
26.0
Min
2.1
0
12.0
Typ
120-035X-000G
Max
16.0
1.0
Unit
µs
µs
µs
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