EM357-RTR Ember, EM357-RTR Datasheet - Page 220

• Manufacturer Part Number: EM357-RTR
• Description: IC RF TXRX ZIGBEE 192KB 48QFN
• Manufacturer: Ember

Specifications of EM357-RTR

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 26mA
• Current - Transmitting: 31mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1011-2

15 Flash Patch and Breakpoint (FPB)
The EM35x integrates the standard ARM
breakpoints. The FPB also provides support for remapping of specific instruction or literal locations from flash
memory to an address in RAM memory. The FPB contains:
The FPB contains a global enable, but also individual enables for the eight comparators. If the comparison for
an entry matches, the address is remapped to the address defined in the remap register plus and offset
corresponding to the comparator that matched. Alternately, the address is remapped to a breakpoint
instruction. The comparison happens on the fly, but the result of the comparison occurs too late to stop the
original instruction fetch or literal load taking place from the flash space. The processor ignores this
transaction, however, and only the remapped transaction is used.
Memory Protection Unit (MPU) lookups are performed for the original address, not the remapped address.
Unaligned literal accesses are not remapped. The original access to the bus takes place in this case.
The FPB is designed for use with advanced debug tools, available from multiple vendors. Altering FPB
configuration may conflict with the operation of advanced debug tools.
For further information on the FPB, contact Ember support for the ARM
Manual, the ARM
Reference Manual, and the ARM
Two literal comparators for matching against literal loads from flash space, and remapping to a
corresponding RAM space.
Six instruction comparators for matching against instruction fetches from flash space, and remapping to a
corresponding RAM space. Alternatively, the comparators can be individually configured to return a
breakpoint instruction to the processor core on a match, implementing hardware breakpoint capability.
®
CoreSight
TM
Components Technical Reference Manual, the ARM
®
v7-M Architecture Application Level Reference Manual.
®
Flash Patch and Breakpoint (FPB). The FPB implements hardware
Final
15-1
®
Cortex
EM351 / EM357
TM
®
-M3 Technical Reference
v7-M Architecture
120-035X-000G